Koninklijke Philips Corporation N.v.

Nxp B.v.

Philips Electronics North America Corporation

Neil Edward Birns

William J Slivkoff

Richard Fabbri

Craig A MacKenna

Hong Bin Hao

Ori K Mizrahi-Shalom

William J Silvkoff

Jie Zheng

Andre Gunther

Farrell Lynn Ostler

Rob Cosaro

Gregory K Goodhue

Domenico Liberti

Hartmut Habben

Ka Leung Ling

Santanu Roy

Kevin A Sholander

Peter Hank

Mathius Muth

A temperature compensated, auto tunable, frequency locked loop oscillator includes, in one embodiment, an oscillator configured to generate a clock-signal with a frequency fclk based on a control voltage vc, and a frequency-to-voltage (f/v) converter coupled to the oscillator, which is configured to generate a first voltage vfb with a magnitude based on frequency fclk. A controller is also included and coupled between the oscillator and the f/v converter. The controller is configured to control the magnitude of the control voltage vc based on the first voltage vfb.

Temperature compensated auto tunable frequency locked loop oscillator

A counter/timer circuit and a method of operating the counter/timer circuit are described. In one embodiment, a method of operating a counter/timer circuit involves determining a match condition by comparing a count value of the counter/timer circuit with a value stored in a match register of the counter/timer circuit and delaying an assertion of the match condition based on a value programmed in a match companion register of the counter/timer circuit. The match companion register is associated with the match register. Other embodiments are also described.

Timer match dithering

A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.

Universal counter/timer circuit

A device that supports a plurality n of message objects, including a plurality of registers associated with each message object, including at least one object match ID register that contains a multi-bit object match ID field, and at least one object mask register that contains a multi-bit object mask field; and, a CAN/CAL module that processes incoming messages. The CAN/CAL module assembles a multi-bit screener ID from selected bits of each incoming message to be acceptance filtered, compares the bits comprising the screener ID with corresponding bits of the object match ID field associated with each of at least designated ones of the message objects, disregarding any bits of each object match ID field that are masked by corresponding bits of the associated object mask field, and then determines whether any of the comparisons results in a match.

CAN device featuring advanced can filtering and message acceptance

A CAN device that supports a plurality n (where n&gE;3) of message objects, including a plurality of registers associated with each message object, including at least one object match ID register that contains a multi-bit object match ID field, and at least one object mask register that contains a multi-bit object mask field; and, a CAN/CAL module that processes incoming messages. The CAN/CAL module assembles a multi-bit screener ID from selected bits of each incoming message to be acceptance filtered, compares the bits comprising the screener ID with corresponding bits of the object match ID field associated with each of at least designated ones of the plurality n of message objects, disregarding any bits of each object match ID field that are masked by corresponding bits of the associated object mask field, and then determines whether any of the comparisons results in a match. Any selected one or more bits of the object match ID field associated with each of the plurality n of message objects can be set to '1' or '0', and any selected one or more bits of the object mask field associated with each of the plurality n of message objects can be set to &lsquo;1&rsquo; or &lsquo;0&rsquo; in order to mask any selected one or more bits of the associated object match ID field, whereby the combination of the object match ID field and the object mask field associated with each of the plurality n of message objects constitutes a fully programmable match and mask filter. The CAN/CAL module has the capability to perform acceptance filtering on incoming messages constituting either standard or extended CAN frames. If more than one match is detected, a lowest-numbered (or, alternatively, highest-numbered) one of the message objects is designated to be the matching message object.

Can device featuring advanced can filtering and message acceptance

A CAN microcontroller that supports a plurality of message objects, including a processor core that runs CAN applications, and a CAN/CAL module that processes incoming messages, and a data memory. The data memory includes a first memory segment that provides a plurality of message buffers associated with respective ones of the message objects, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects. The memory-mapped registers for each message object contain respective command/control fields for configuration and setup of that message object. The CAN microcontroller further includes a memory interface unit that permits the processor core and the CAN/CAL module to concurrently access a different respective one of the first and second memory segments, and that arbitrates access to the same one of the first and second memory segments when the processor core and the CAN/CAL module request concurrent access to the same one of the first and second memory segments. In a second embodiment, the data memory includes a first memory space that is located on an integrated circuit chip on which the CAN microcontroller and the CAN/CAL module are incorporated, and a second memory space that is located off the integrated circuit chip. The first memory space includes a first memory segment that provides at least a portion of a message buffer memory space, and a second memory segment that provides a plurality of memory-mapped registers for each of the message objects. With this second embodiment, the CAN microcontroller further includes a memory interface unit that permits the processor core and the CAN/CAL module to concurrently access a different respective one of the first and second memory spaces, that permits the processor core and the CAN/CAL module to concurrently access a different respective one of the first and second memory segments, and that arbitrates access to the second memory space and that arbitrates access to the same one of the first and second memory segments when the processor core and the CAN/CAL module request concurrent access to the second memory space or to the same one of the first and second memory segments.

Can microcontroller that permits concurrent access to different segments of a common memory by both the processor core and the DMA engine thereof

A method for conserving power in a CAN microcontroller that includes a processor core and a CAN/CAL module that includes a plurality of sub-blocks that cooperatively function to process incoming CAL/CAN messages, which method includes the steps of placing the processor core in a power-reduction mode of operation (e.g., a sleep or idle mode of operation), placing the CAN/CAL module in a power-reduction mode of operation, and activating the CAN/CAL module to process an incoming CAL/CAN message (e.g., to perform automatic hardware assembly of a multi-frame, fragmented CAL/CAN message), thereby terminating the power-reduction mode of operation thereof, while the processor core is in its power-reduction mode of operation. In a preferred embodiment, the CAN/CAL module automatically assembles incoming, multi-frame, fragmented messages while the processor core remains in its power-reduction mode of operation, and the CAN/CAL module generates a message-complete interrupt in response to completion of assembly of the multi-frame, fragmented message, whereby the terminating step is executed in response to the message-complete interrupt. In another embodiment, the method includes the steps of placing the entire CAN microcontroller, including both the processor core and the CAN/CAL module in a power-down mode of operation, detecting receipt of an incoming message, and activating the CAN/CAL module in response to the detecting step to process the incoming message (e.g., to perform automatic hardware assembly of a multi-frame, fragmented CAL/CAN message), thereby terminating the power-down mode of operation of the CAN/CAL module, without terminating the power-down mode of operation of the processor core.

Method for conserving power in a can microcontroller and a can microcontroller that implements this method

A CAN microcontroller that supports a plurality of message objects, the CAN microcontroller including a processor core that runs CAN applications, a CAN/CAL module that processes incoming messages, and a plurality of message buffers associated with respective ones of the message objects, each message buffer having a size and a location that are programmable. The CAN microcontroller also includes a data memory space. Preferably, the plurality of message buffers are located in the data memory space, which may include both an on-chip portion and an off-chip portion. The plurality of individual message object registers associated with each of the message objects contain fields of command/control information that facilitate configuration and setup of that message object. Preferably, the plurality of individual message object registers associated with each message object include at least one buffer size register that contains a message buffer size field that enables the size of the message buffer associated with that message object to be programmed, and at least one buffer location register that contains a message buffer location field that enables the location of the message buffer associated with that message object to be programmed.

Can microcontroller that employs reconfigurable message buffers

A CAN microcontroller that supports a plurality of uniquely-numbered message objects, that includes a processor core that runs CAN applications, a plurality of message buffers associated with respective ones of the message objects, and a CAN/CAL module. The CAN microcontroller further includes a plurality of individual message object registers associated with each message object, including at least one control register that contains an interrupt-enable control bit, a receive enable bit, and a transmit enable bit. The CAN microcontroller also includes a plurality of global message object control registers, including at least one message complete status register that contains a plurality of status flag bits for respective ones of the message objects, at least one interrupt flag register that contains a receive complete interrupt flag bit and a transmit complete interrupt flag bit, and a message complete info register that contains a plurality of message object identification bits and a status bit. The CAN/CAL module includes a message handling function that automatically transfers successive frames of an incoming multi-frame message to the message buffer associated with a corresponding message object; an end-of-message detection function that detects an end-of-message condition which occurs when the last frame of the accepted incoming multi-frame message has been stored in the message buffer associated with the corresponding message object; and, an end-of-message detection handling and interrupt generation function that, in response to the detection of the end-of-message condition: sets the status flag bit contained in the at least one message complete status register associated with the corresponding message object; sets the receive complete interrupt flag bit contained in the at least one interrupt flag register, if the interrupt-enable control bit contained in the at least one control register associated with the corresponding message object is set; and, sets the status bit contained in the message complete info register, if the interrupt-enable control bit contained in the at least one control register associated with the corresponding message object is set.

End-of-message handling and interrupt generation in a CAN module providing hardware assembly of multi-frame CAN messages

A method for use in a CAN device (e.g., a CAN microcontroller) that includes a processor core and hardware external to the processor core (e.g., a DMA engine) that writes message data into a designated message buffer for ensuring integrity of the message data stored in the designated message buffer. The method includes providing a three-state semaphore to indicate a current access status of the designated message buffer, the three-state semaphore having a first state indicative of the hardware external to the processor core starting to write new message data into the designated message buffer, a second state indicative of the hardware external to the processor core having finished writing the new message data into the designated message buffer, and, a third state indicative of the processor core starting to read message data from the designated message buffer. The processor core determines whether the designated message buffer is ready to be accessed based on the current state of the semaphore. The processor core, after determining that the designated message buffer is ready to be accessed, reads the message data from the designated message buffer. After the processor core has finished reading the message data from the designated message buffer, it checks the current state of the semaphore to determine whether it has changed to a different state during the time that the processor core was reading the message data from the designated message buffer. If the processor core determines that the current state of the semaphore changed during the time that the processor core was reading the message data from the designated message buffer, it again determines whether the designated message buffer is ready to be accessed, based on the current state of the semaphore. After again determining that the designated message buffer is ready to be accessed, the processor core again reads the message data from the designated message buffer.

Semaphore coding method to ensure data integrity in a can microcontroller and a can microcontroller that implements this method

A CAN microcontroller that supports a plurality of message objects, and that includes a CAN processor core, a plurality of message buffers associated with respective ones of the message objects, a CAN/CAL module that processes incoming messages that include a plurality of frames and a plurality of message object registers, including at least one buffer size register that contains a message buffer size value, and at least one buffer location register that contains an address pointer. The CAN/CAL module includes a message handling function that transfers successive frames of the current incoming message to the message buffer associated with a selected one of the message objects designated as a receive message object for the current incoming message an address pointer increment function. The CAN/CAL module further includes a frame status detection function, and a buffer-status detection function that retrieves the incremented address pointer value, retrieves the message buffer size value from the at least one buffer size register associated with the designated receive message object, and decodes the retrieved message buffer size value into a buffer-size mask, and determines a message buffer-fullness status of the message buffer associated with the designated receive message object using the retrieved incremented address pointer value and the buffer-size mask.

Use of buffer-size mask in conjunction with address pointer to detect buffer-full and buffer-rollover conditions in a CAN device that employs reconfigurable message buffers

A CAN microcontroller that supports a plurality of message objects, and that includes a processor core that runs CAN applications, a plurality of message buffers associated with respective ones of the message objects, a CAN/CAL module that processes incoming messages that include a plurality of frames, each frame having a maximum number n of data bytes, and a plurality of message object registers associated with each of the message objects, including at least one buffer size register that contains a message buffer size value that specifies the size of the message buffer associated with that message object, and at least one buffer location register that contains an address pointer that points to an address of the storage location in the message buffer associated with that message object where the next data byte of the current incoming message is to be stored. The CAN/CAL module includes a message handling function that transfers successive frames of the current incoming message to the message buffer associated with a selected one of the message objects designated as a receive message object for the current incoming message, a frame status detection function that detects whether or not the current frame of the current incoming message is the final frame of the current incoming message, and a buffer-full detection function. The buffer-full detection function, in response to a detection that the current frame of the current incoming message is not the final frame of the current incoming message, determines the number of available bytes of remaining storage capacity in the message buffer associated with the designated receive message object for the current incoming message, and declares a message buffer-full condition if the determined number of available bytes is less than the maximum number n of data bytes. The CAN/CAL module further includes a message buffer-full interrupt generator function that generates a message buffer-full interrupt to the processor core in response to a declaration of a message buffer-full condition.

Message buffer full handling in a CAN device that employs reconfigurable message buffers

A CAN microcontroller that supports a plurality of message objects, including a processor core that runs CAN applications, a CAN/CAL module that processes incoming messages, and a data memory space. The data memory space includes a plurality of message buffers associated with respective ones of the message objects, and a dedicated RAM memory space that contains a plurality of memory-mapped registers associated with each of the message objects. The plurality of memory-mapped registers associated with each message object correspond to respective command/control fields for facilitating configuration and setup of that message object. Each of the memory-mapped registers is mapped to a respective storage location within the dedicated RAM memory space. In one embodiment, the dedicated RAM memory space encompasses a plurality of separate RAM modules, each RAM module being dedicated to a respective one of the command/control fields. The memory-mapped registers corresponding to a respective one of the command/control fields are located in respective, designated addressable memory storage locations within the separate RAM module dedicated to that command/control field, with/a different addressable memory storage location being designated for each respective one of the message objects. In one particular implementation, all of the memory-mapped registers corresponding to a respective one of the command/control fields are located in a respective one of the separate RAM modules dedicated to that command/control field.

Can microcontroller that utilizes a dedicated RAM memory space to store message-object configuration information

A reset device is disclosed which is part of a micro-controller formed on an integrated circuit. The reset device has a counter which outputs a count enable signal after counting a predetermined number of counts. In response to an input reset signal, an input device of the reset device provides a start signal to the counter for initiating count-down thereof. An output device outputs an output reset signal in response to the start signal and the count enable signal. The start signal is inhibited by a control signal, which is provided from a control device in response to an external reset signal received at an input pin of the micro-controller. The input device includes an AND gate which receives the input reset signal, an inverted delayed version of the input reset signal, and the disable signal. The reset device further includes an OR gate which receives the start signal and the count enable signal to provide an input signal to the output device for generation of the output reset signal. Another OR gate receives the outputs the counter and provides the count enable signal.

Growing community of inventors

Cupertino, CA, United States of America

Neil Edward Birns