Peregrine Semiconductor Corporation

Freescale Semiconductor,inc.

Neil Calanca

Jaroslaw E Adamski

Vikas Sharma

Robert J Broughton

Chris Olson

Jyoti P Mondal

Peter Bacon

Matthew Richard Miller

Joseph Farzin Ahadian

Joseph P Golat

Yang Li

Yan Cui

James Bonkowski

An amplifier circuit having an improved inter-stage matching network and improved performance. In one embodiment, an RF signal source having an output impedance Zis approximately impedance matched through an inductive tuning circuit to a power amplifier having an input impedance Z. The inductive tuning circuit includes a tunable capacitor element Cand inductive elements L, L, which may be fabricated as stacked conductor coils. Since the capacitance of Cis tunable, impedance matching is available over a broad range of RF frequencies. Also provided are DC isolation between the RF signal source and the power amplifier, coupling of a voltage source to the output of the RF signal source through L, and coupling of a bias voltage to the input of the power amplifier through L

Coupled coils inter-stage matching network

Embodiments of RF switching amplifiers are described generally herein. Other embodiments may be described and claimed.

Method, system, and apparatus for RF switching amplifier

Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters.

Dual path level shifter

Biasing methods and devices for power amplifiers are described. The described methods and devices use the power amplifier output voltage to generate bias voltages. The bias voltages are obtained using rectifiers and voltage dividers. The described biasing methods and devices can be used with class-E power amplifiers.

Biasing methods and devices for power amplifiers

A novel RF power amplifier integrated circuit (PA IC), unit cell, and method for amplifying RF signals are disclosed. One embodiment of a PA IC includes at least two linear arrays comprising transistor device units, and at least one linear array comprising capacitors. The transistor device units include source nodes that are jointly coupled to a source bus, and selected gate nodes that are jointly coupled to a gate bus. First electrodes of the capacitors are also jointly coupled to the source bus, and second electrodes of the capacitors are jointly coupled to the gate bus. Each linear array comprising capacitors is disposed between at least two linear arrays comprising transistor device units. In one embodiment, the PA IC includes unit cells. In some embodiments, each unit cell comprises two transistor device units and one or more capacitors. The capacitors are disposed between the transistor device units. The unit cells are disposed in linear arrays so that the transistor device units are disposed in linear arrays and the capacitors are disposed in linear arrays.

RF power amplifier integrated circuit and unit cell

In a particular embodiment, an oscillator adjustment circuit is disclosed. The oscillator adjustment circuit includes a resonator portion comprising a capacitive element coupled to an inductive element and a signal balancing portion comprising a secondary coil of the transformer. The inductive element comprises a primary coil of a transformer. The secondary coil has a grounded center tap.

Transformer coupled oscillator and method

A variable gain control amplifier () and method provides a substantially constant input impedance and output impedance, and provides a substantially constant noise figure and third order harmonic. The variable gain control amplifier () includes an amplifier stage including at least a first intermediate fixed gain stage () operative to produce a first intermediate signal () in response to the input signal (). The variable gain control amplifier () further includes at least a second intermediate fixed gain stage () operative to produce an output signal () in response to the first intermediate signal (). A feedback circuit () is operative to produce a gain control signal () in response to the output signal (). A gain control circuit () is coupled to the at least first intermediate fixed gain stage () and the second intermediate fixed gain stage (), and receives the gain control signal () to control an amplitude of the intermediate signal ().

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Crown Point, IN, United States of America

Neil Calanca