Sun Microsystems, Inc.

Other

Digital Equipment Corporation

Neil C Wilhelm

Hans Eberle

J Duane Northcutt

Robert Yung

Judson S Leonard

Robert J Drost

James Gregory Hanko

David D Lee

Alan T Ruberg

Nils Gura

Lawrence Llewelyn Butcher

Gerard A Wall

Derek McAuley

David Pessel

The invention provides a central office metaphor to computing, where features and functions are provided by a one or more servers and communicated to an appliance terminal through a network. Data providers are defined as 'services' and are provided by one or more processing resources. The services communicate to display terminals through a network, such as Ethernet. The terminals are configured to display data, and to send keyboard, cursor, audio, and video data through the network to the processing server. Functionality is partitioned so that databases, server and graphical user interface functions are provided by the services, and human interface functionality is provided by the terminal. Communication with the terminals from various services is accomplished by converting disparate output to a common protocol. Appropriate drivers are provided for each service to allow protocol conversion. Multiple terminals are coupled to the network. Users can enable their unique session at any one of the terminals by inserting a 'smart card' into a card reader. Removing the card disables the session. Re-inserting the card into the same or any other terminal re-enables the session.

Computer architecture having a stateless human interface device and methods of use

A computer system coupled with a pipelined network includes a plurality of initiator nodes coupled to send packets into the network. A plurality of target nodes receive packets sent into the network. The network uses a plurality of pipeline stages to transmit data across the network. Each pipeline stage consumes a known time period, which provides for a predetermined time period for transmission for each packet that is successfully sent from one of the initiator nodes to one of the target nodes. The pipelined network is synchronous in that boundaries of all the pipeline stages are aligned. The pipeline stages include at least an arbitration stage to obtain a path through the network, a transfer stage during which a data packet is transmitted, and an acknowledge stage during which successful transmission of a packet is indicated by the target. To simplify network design, all the pipeline stages are implemented to have equal length.

Method and apparatus for a pipelined network

A data network provides independent transmission channels for transmitting high bandwidth and low latency information data packets between nodes. The data information packets are organized into at least two groups of data packets according to predetermined criteria. The predetermined criteria includes a latency budget of the data packets, the size of the data packets and the type of operation. The low latency channel is also coupled to transmit control information relating to network protocol.

Data network with independent transmission channels

A switched network includes a buffer-less switch coupling the sending nodes and the receiving nodes. The switch transmits packets successfully delivered to the receiving nodes through the buffer-less switch with a fixed forwarding rate. The switched network resolves conflicts in requests for a transmission path on the switch from multiple packets by allocating the transmission path to a first requester in time for the transmission path. If multiple requests for a switch resource collide by requesting the switch resource at the same time, one of the requests is selected as a winner and the packet or packets associated with the remaining requests are dropped. The winning packet may be selected on a random basis or a round robin basis or based on some other criteria. The requests from transmission paths may be contained with the packets sent into the network and extracted on entry of the packet into the network.

Switched network for low latency communication

Method and circuitry for improving noise immunity of differential data channels that use a shared reference channel by substantially matching their respective noise transfer functions. Any combination of various circuit parameters at the reference channel including termination resistance R, channel impedance Zo, and parasitic inductance L are scaled to substantially match the noise transfer function of the reference channel to that of the data channels.

Method and apparatus for reducing noise in communication channels having a shared reference signal

The system described provides a reconfigurable serial interconnection among a processor, whether in a workstation or a server, and user class I/O devices, such as video display terminals, storage devices, and other peripherals. Sustainable I/O throughput of 1 Gbps or more supports the needs of display and video input devices. In addition the system allows hot plug-and-play of user class I/O devices.

High speed serial communications link for desktop computer peripherals

A processor is disclosed. The processor includes a processing unit with a plurality of pipelines. Each of the pipelines execute instructions which may define source register values and destination register values from a register file. A plurality of memories is also provided, each associated with one of the plurality of pipelines respectively. A coherency mechanism is provided to maintain coherency among the register values in the plurality of pipelines and their associated memories. In one embodiment, each memory associated with the plurality of pipelines is a register cache. Each register cache stores register values that were just used or will soon be needed by the instructions that have or will be executed on the pipeline associated with the register cache. A variety of coherency mechanisms may be used to transfer register values from register cache to register cache and maintain coherency among the register values in the plurality of register caches. The coherency protocols include, but are not limited to ownership protocols, snooping protocols and a new protocol that permits only one addressable valid copy of a register value among all the register caches and the register file at a time.

Processor having a plurality of pipelines and a mechanism for

A processor is disclosed. The processor relates to a processor having a register file of registers and a dispatch unit capable of issuing up to (i) instructions of a program per cycle to an execution unit having (z) pipelines, wherein some of the instructions specify certain ones of the registers in the register file as source operands and designate certain ones of the registers in the register file as destination registers. The processor also includes a memory for storing the registers of the register file, the memory having (N) access ports configured to access up to (N) registers per cycle, where (N) is less than a maximum number of register values that may need to be accessed during a cycle.

Computer processor having a register file with reduced read and/or write

A data processing system is described in which the available technology is used to provide high performance. The high performance is achieved by having a four-level pipeline for the central processing system, a simplified instruction set and an interface with the coprocessor unit that has a simple and efficient interface with the normal instruction execution. The apparatus implementing the central processing system is closely connected to the instruction set. A discussion of the implementation of the data processing system is provided.

Apparatus and method for a pipelined central processing unit in a data

In a data processing system with a central processing unit having a pipelined mode of operation, apparatus and method are disclosed for synchronizing the operation of a coprocessor unit with the remainder of the central processing unit, the remainder of the central processing unit being implemented for pipelined execution of instructions. Because the coprocessor unit performs manipulations of logic signal groups that require a longer time for execution than the manipulation contemplated by the requirements of pipelined instruction execution, the coprocessor unit must be synchronized with an instruction stream adapted to use the rigidly controlled pipelined implementation. In order to synchronize the coprocessor unit with the remainder of the central processing unit, the instructions controlling the operation of the coprocessor unit have two portions. A first portion of a coprocessor instruction designates the storage location into which the result of the previous operation is to be stored, while the second portion of the coprocessor instruction defines the operation to be performed on the operand in a designated location.

Apparatus and method for synchronization of a coprocessor unit in a

A telephone loud-speaker system for use with telephones having a handset includes a chassis with a cradle for receiving the handset. The cradle is movable between a first position whereat the telephone's switch buttons are depressed, and a second position allowing the switch buttons to raise and actuate the telephone's electrical circuitry. Microphone, speaker and amplification devices permit use of the system without removing the handset from the cradle, without modification to telephone, and without requiring additional counter space.

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Menlo Park, CA, United States of America

Neil C Wilhelm