Skyworks Solutions, Inc.

Zarbana Digital Fund LLC

Philsar Semiconductor Inc.

Neil Birkett

Norm Filiol

Thomas Riley

Florinel G Balteanu

William Martin Snelgrove

Trevor Noel Yensen

James Cherry

Phil Guillemette

Daniel Payer

The invention relates generally to the field of wireless communications and more particularly to a method of and device for detecting the presence of a received data packet in a digital receiver. The present invention proposes a simplified method of correlation by removing dependency on the amplitude fluctuations while at the same time maintaining phase relevancy. The key advancement involves mapping the complex quadrature amplitude modulation (QAM) preamble to a quantized phase shift keying (PSK) constellation before application to a matched complex correlator. The proposed process essentially 'amplitude normalizes' the input signal without the use or complexity associated with a divider. This simplified normalization scheme makes the packet detection algorithm robust against amplitude variations in the input signal, while still allowing for good correlation output. In applications where interference is superimposed on the I/Q input signals, the invention improves the detection capability over automatic gain control (AGC) normalization methods.

Method for amplitude insensitive packet detection

A method of and device for automatic gain control (AGC) incorporates digitally controlled variable gain amplifiers (VGAs). An AGC circuit comprises multiple AGC stages, where each of the stages comprises: respective I and Q VGAs; a detector for detecting respective I and Q output signals received from the respective I and Q VGAs; an analogue to digital converter for converting the detected I and Q output signals; and a digital engine for adjusting the respective I and Q VGAs for differences between the detected I and Q output signals and a reference signal. Using staggered AGCs incorporating respective I and Q VGAs splits the total dynamic range between n stages, allowing for reduced gain requirements in the VGAs. Using digital control for setting the VGA gains reduces analogue variations and I/Q gain imbalances. Using multiple update rates or magnitudes in the VGA control improves dynamic settling time.

Staggered AGC with digitally controlled VGA

A digital demodulator which coherently demodulates a low-IF or zero-IF complex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provide independent phase/frequency and amplitude outputs. The CPLL exhibits in first order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low FM modulation indexes whereby the incoming frequency drift may be larger than the frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.

Complex phase-locked loop demodulator for low-IF and zero-IF radio receivers

A low power IF strip architecture suitable for Zero-IF (ZIF) or low-IF (LIF) radio receivers for filtering and amplifying a received signal. The apparatus includes a plurality of sequentially connected complex filter/amplifier stages. Each stage includes a complex filter having one or more poles and an automatic gain controlled amplifier (AGC). Each AGC may be feedback or feedforward with fixed minimum and maximum gains. Each stage further includes a control circuit that produces a gain control signal for controlling the amplifier gain within the fixed minimum and maximum gains as a function of a projected amplitude level. The received signal passes through multiple stages of filtering and controlled amplification to attenuate the interfering signal and amplify the desired signal. This is done at a restricted level in each stage such that the circuits in the stages operate at efficient power saving levels. The individual gain control signals from each stage are summed in a received signal strength indicator to provide the overall gain of the apparatus. The overall gain when taken with the amplitude of the apparatus output signal determines the original strength of the desired received signal.

Complex filtering/AGC radio receiver architecture for low-IF or zero-IF

A digital demodulator which coherently demodulates a low-IF or zero-IF complex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provide independent phase/frequency and amplitude outputs. The CPLL exhibits in first order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2 or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low FM modulation indexes whereby the incoming frequency drift may be larger than the frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.

A method and apparatus for dynamically generating multiple level decision thresholds of an M-ary demodulated signal for decoding the signal. The threshold values are obtained by obtaining the maximum and minimum peak values of the demodulated M-ary signal, averaging these peak values and subsequently processing these averaged values to establish the threshold for the particular M-ary signal. Infinite impulse response filters may be advantageously used in the averaging process and these filters may be preloaded with maximum and minimum peak values such that decision threshold levels may be generated immediately after receiving the M-ary demodulated signal.

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Richmond, CA, United States of America

Neil Birkett