Advanced Micro Devices Corporation

Ati Technologies Ulc

Nehal Patel

Lu Lu

Gia Tung Phan

Shantanu Sarangi

Christian Warling

Dong Zhu

Zang SongGan

James A Ott

The disclosed device includes an input, an output and multiple flops serially connected between the input and the output. The device also includes a bypass circuit coupled to the input and the output and a control circuit. The control circuit can enable, in response to a first trigger, the flops to shift data to the output. In response to a second trigger, the control circuit can disable the flops and enable the bypass circuit to shift data from the input to the output. The flops can be part of a chain of flops. Various other methods, systems, and computer-readable media are also disclosed.

Increased shift frequency for multi-chip-module scan

A disclosed technique includes based on a clock pattern, determining an enable configuration for setting enable signals for one or more multi-cycle paths of a hardware logic network; controlling a selector to set the enable configuration for the one or more multi-cycle paths; and executing testing operations for the hardware logic network with the one or more multi-cycle paths enabled according to the enable configuration.

Testing multi-cycle paths based on clock pattern

A computer-implemented method for enabling debugging can include receiving, at a peripheral device connected through an expansion socket to a base CPU platform, a scan dump instruction from a network computing device connected to the base CPU platform across a network connection and executing, by a System-on-Chip at the peripheral device in response to the scan dump instruction, a debugging procedure. The debugging procedure can include capturing a snapshot of memory of the peripheral device and transmitting the snapshot to the network computing device through memory addresses that have been assigned to memory-mapped input/output. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for enabling debugging

A disclosed technique includes clock gating a plurality of data elements of a first clock domain of a scan dump network; outputting data from a plurality of data elements of a second clock domain of the scan dump network; clock gating the plurality of data elements of the second clock domain; and outputting data from the plurality of data elements of the first clock domain.

Low power and high speed scan dump

A system, method, and tangible computer readable medium for chip debug is disclosed. For example, the system can include a plurality of functional blocks, a debug path, and a debug bus steering module. The debug path couples the plurality of functional blocks in a daisy chain configuration, where an end functional block from the plurality of functional blocks is at an end of the daisy chain configuration. The debug bus steering module is configured to pass one or more debug signals associated with a first functional block from the plurality of functional blocks along the debug path to the end functional block while a second functional block from the plurality of functional blocks performs one or more power gating cycles.

Growing community of inventors

Sunnyvale, CA, United States of America

Nehal Patel