International Business Machines Corporation

Neelesh Govindaraya Pai

Michael Richard Ouellette

Michael Thomas Fragano

Jeffery Howard Oppold

James Norris Dieffenderfer

Joel Abraham Silberman

Thomas Philip Speier

William Robert Reohr

Francois Ibrahim Atallah

Jeffrey Herbert Fischer

Ciaran J Brennan

Steven Michael Eustis

Jeremy Paul Rowland

David J Wager

Adam G Moldovan

Kevin M Tompsett

Daniel Stephen Geise

A method for providing memory cells that allow multiple variations of metal level assignments for bitlines and wordlines is disclosed. A memory cell includes two cell elements. The first and second cell elements are identically processed up to a metal-1 layer. The first cell element is subsequently processed with bitlines on a metal-2 layer and wordlines on a metal-3 layer. Next, the second cell element is processed with bitlines on the metal-3 layer and wordlines on the metal-2 layer.

Method for providing memory cells capable of allowing multiple variations of metal level assignments for bitlines and wordlines

A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.

Method and apparatus for test and repair of marginally functional SRAM cells

A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for accessing one or more of the memory cells in response thereto. The random access memory circuit further comprises a plurality of sense amplifiers operatively coupled to the memory cells, the sense amplifiers being configurable for determining a logical state of one or more of the memory cells. A controller coupled to at least a portion of the sense amplifiers is configurable for selectively operating in at least one of a first mode and a second mode. In the first mode of operation, the controller enables one of the sense amplifiers corresponding to the input address and disables the sense amplifiers not corresponding to the input address. In the second mode of operation, the controller enables substantially all of the sense amplifiers. The memory circuit advantageously provides an adaptable latency by controlling the mode of operation of the circuit.

Random access memory having an adaptable latency

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Williston, VT, United States of America

Neelesh Govindaraya Pai