Intel Corporation

Neelam Chandwani

Stephen T Palermo

Mohan J Kumar

Sarathy Jayakumar

Lokpraveen B Mosur

Candy Yiu

Nageen Himayat

Dave A Cavalcanti

Harry G Skinner

Jeffrey R Foerster

Ned M Smith

Francesc Guim Bernat

Johanna M Swan

Michael A Rothman

Adel A Elsherbini

Kshitij Arun Doshi

Thorsten Clevorn

Shawna M Liff

Efraim Rotem

Eliezer Weissmann

Rita H Wouhaybi

Dmitri E Nikonov

Krishnakanth Venkata Sistla

Paul S Diefenbaugh

Tanay Karnik

Srikathyayani Srikanteswara

Bishwarup Mondal

Timothy Verrall

Srihari Makineni

Jeremy J Shrall

Guy M Therien

Robert E Gough

Gerald S Pasdast

Krishna Bharath

Avik Sengupta

Marcos Emanuel Carranza

Mark Doran

Anil Aggarwal

Andrew D Henroid

Jose Andy Vargas

Niall D McDonnell

Yi Zhang

Udayan Mukherjee

Chetan Hiremath

Rakesh Dodeja

Shubha Bommalingaiahnapallya

Brent Elliott

Mikhail T Galeev

Shadi Iskander

Susruth Sudhakaran

Rajesh Gadiyar

Wen Wei

Adwait Purandare

Benjamin Grewell

Rany T Elsayed

Anthony Ambrose

Durgesh Srivastava

Julien Sebot

Robert J Munoz

Shrikant M Shah

Thijs Metsch

Cesar Martinez-Spessot

Mustafa Akdeniz

Jesus Martinez

Nevine Nassif

Valerie J Parker

Kevin W Bross

Kin-Hang W Cheung

Atul Kwatra

Santosh Balakrishnan

Uzair Qureshi

Pinkesh J Shah

Carleton L Molnar

Weiqiang Ma

Yean Kee Yong

Jason K Smith

Udayan Mukheriee

Rany ElSayed

Ranjit Cavatur

Michael Beadle

Chetan D Hiremath

An apparatus for use in an O-RAN base station includes processing circuitry. To configure the O-RAN base station for signal processing in an O-RAN network, the processing circuitry is to decode an SRS and a DMRS in a UL stream received from at least one UE. Channel estimation is performed based on the SRS to obtain a channel estimate matrix of channel estimates associated with reception of the UL stream. A noise covariance is generated using the DMRS. Beamforming weights are determined using the channel estimate matrix and the noise covariance. Beamforming is performed on UL data corresponding to the UL stream to generate beamformed data streams. The beamforming is based on applying the beamforming weights to the UL data.

Beamforming and interference mitigation techniques for massive MIMO uplink and downlink in O-RAN 7-2 compatible base stations

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

Fine-grained disaggregated server architecture

An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.

Systems, methods, and apparatus for workload optimized central processing units (CPUS)

Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.

Frequency scaling for per-core accelerator assignments

Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.

Satellite 5G terrestrial and non-terrestrial network interference exclusion zones

An apparatus of a wireless device, such as a user equipment (UE), can include processing circuitry configured to perform one or more of the handover-related techniques disclosed herein. For example, when associated with moving with a plurality of mobile devices from coverage of a first cell to a second cell, the processing circuitry can detect the second cell. One or more parameters of the second cell can be measured. The one or more parameters can be communicated to one or more other mobile devices of the plurality of mobile devices.

Handover-related technology, apparatuses, and methods

In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Computing platform interface with memory management

A method to reduce memory power consumption for a computing platform includes inspecting an operating parameter associated with a resource of the computing platform that is updated by the resource of the computing platform during runtime of the computing platform. Memory power utilization is then predicted for the computing platform during the runtime of the computing platform based at least in part on the operating parameter. A current power state of at least one memory module resident on the computing platform is transitioned to one of a plurality of power states based on the predicting of the memory power utilization.

Predict computing platform memory power utilization

Described herein are a method and an apparatus for reducing power consumption of memories by monitoring the power states of the memories via an operating system. The method comprises reading counter values corresponding to power states of each memory of a plurality memories; computing a power state usage corresponding to the power states of each memory of the plurality, the computing based on the counter values; determining whether the power state usage exceeds a predetermined threshold usage; and adjusting current and future usage of each memory of the plurality in response to determining that the power state usage exceeds the predetermined threshold usage.

Method and apparatus for reducing power consumption for memories

Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel.

Method and apparatus for reducing power consumption in multi-channel memory controller systems

A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.

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Portland, OR, United States of America

Neelam Chandwani