Motorola Corporation

Freescale Semiconductor,inc.

Neal W Hollenbeck

Lawrence Edwin Connell

William J Roeckner

Michael Lee Bushman

Daniel P McCarthy

Kenneth Allen Paitl

David D Kang

Patrick Lee Rakers

Walter S Czarnocki

Kenneth R Haddad

Donald B Lemersal, Jr

Timothy T Rueger

Daniel Patrick McCarthy

James W Caldwell

Timothy Rueger

Walter Czarnocki

A variable attenuator and method of attenuating a signal is presented. The variable attenuator contains an input that receives an input signal to be attenuated. A voltage divider between a resistor and parallel MOSFETs provides the attenuated input signal. The MOSFETs have different sizes and have gates that are connected to a control signal through different resistances such that the larger the MOSFET, the larger the resistance. The control signal is dependent on the output of the attenuator. The arrangement extends the linearity of the attenuation over a wide voltage range of the control signal and decreases the intermodulation distortion of the attenuator.

Linear voltage controlled variable attenuator with linear DB/V gain slope

A direct digital synthesis circuit () includes a plurality of current sources (), an output circuit (), and a logical multiplier circuit (). The output circuit () provides a synthesized waveform () output and includes a first () and second branch (). The logical multiplier circuit () is operatively coupled to the plurality of current sources () and to the output circuit (). The logical multiplier circuit () is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch () by a determined magnitude and decrease a second current flow through the second branch () by the determined magnitude based on the plurality of signals. The synthesized waveform () is based on the first and second currents.

Direct digital synthesis circuit

A dual mode voltage supply circuit () includes an active mode voltage supply circuit () and a passive mode voltage supply circuit (). The active mode voltage supply circuit () is selectively operative to supply a voltage () based on mode control information (). The active mode voltage supply circuit () is operative to provide a first current capacity. The passive mode voltage supply circuit () is operatively coupled to the active mode voltage supply circuit (). The passive mode voltage supply circuit () is operative to supply the voltage () when the active mode voltage supply circuit () is not supplying the voltage (). The passive mode voltage supply circuit () is operative to provide a second current capacity that is less than the first current capacity.

Dual mode voltage supply circuit

An amplifier, tuner, and method of amplification are provided. The amplifier has a pair of transistors. Each transistor has a control terminal and an output terminal disposed between the transistor and a power supply input. A first network is connected between each power supply input and output terminal. The first network contains a first resistor and a first switch connected in parallel with the first resistor. A second network is connected between the transistors. The second network contains a first and second combination. Each of the first and second combinations contains a second resistor and a second switch connected in parallel with the second resistor. The first and second combinations are connected by a third switch.

High linearity and low noise amplifier with continuously variable gain control

An edge seal structure and fabrication method are described. The edge seal structure includes a high impedance substrate containing a base material and a grounded floating edge seal that is on the substrate but is isolated from the base material. The edge seal contacts a first doped well in the substrate that has the same conductivity type as and is more heavily doped than the base material. The first doped well is in a second doped well that has a different conductivity type than the first doped well. The first and second doped wells and the base material form back-to-back series connected diodes. The wells are effectively connected to power and ground such that the diodes are reverse-biased. The edge seal is formed by a stack of conductive layers, at least some of which are surrounded by a stack of insulating layers.

Edge seal for improving integrated circuit noise isolation

A regulation circuit, incorporated in a single integrated circuit with a first circuit load, which as an input coupled to a power supply which produces a source voltage, and a first output coupled to the first circuit load. The regulation circuit comprises an input capacitor for reducing the magnitude of a voltage change at the first output, and at least a first voltage regulator for producing a predetermined voltage at the first load.

High performance integrated circuit regulator with substrate transient suppression

A high gain wide-band width RF amplifier with automatic bias supply regulation. The load supply is actively adjusted in response to the amplifier's output signal level. At small output signals effective load supply voltage is minimum and at larger output signals the effective load supply voltages is maximized. The amplifier includes a differential pair of field effect transistors (FETs) connected at common source connection and biased by current bias FET which is connected between common source connection and amplifier signal input RFIN. A bias voltage (V ) is applied to the gate of bias device and an automatic gain control voltage (V ) is applied to the gates of differential FET pair . The automatic bias supply circuit is an active load and includes resistors , capacitor and a differential amplifier . Capacitor is connected between the negative input and the output of differential amplifier . A load reference voltage VO is provided to the positive input. Resistor is connected between the output of differential amplifier and the high gain wide-band amplifier output at the drain of FET . Resistor is connected between the output at the drain of FET and the negative input to differential amplifier providing amplifier load signal feedback.

Variable gain amplifier with autobiasing supply regulation

A single ended input differential output amplifier ( ) and integrated circuit including such an amplifier ( ). A pair of load resistors ( ) are connected between a supply voltage (V ) and differential outputs OUTP and OUTM. An inductor ( ) is connected between input RFIN and a source bias voltage V . A first field effect transistor (FET) ( ) is connected, drain to source, between load resistor ( ) at output OUTP and inductor ( ) at RFIN. A second FET ( ) is connected, drain to source, between the second load resistor ( ) at output OUTM and the source bias voltage V . A gate bias voltage V is connected to the gate of FET ( ) and through resistor ( ) to the gate of FET ( ). A coupling capacitor ( ) is connected between the input RFIN and the gate of FET ( ). The gate of FET ( ) may be connected to gate bias voltage V through a second gate bias resistor ( ) and a second coupling capacitor ( ) may couple the source of FET ( ) to the gate of FET ( ), thereby providing common mode rejection for noise, e.g., substrate noise, experienced at inductor ( ).

Single ended input, differential output amplifier

An electronically calibrated sensor (100) includes a sensing element (102) with an output coupled to a signal conditioning circuit (104). The signal conditioning circuit (104) is adapted to be highly computationally efficient and operable for compensating for temperature and part-to-part variation on the sensing element output for providing a useable sensor output signal. The signal conditioning circuit (104) includes an analog-to-digital/digital-to-analog (ADC/DAC) conversion device (112). The ADC/DAC (112) is operable to perform both analog input signal analog-to-digital conversion and digital output signal digital-to-analog conversion. The ADC/DAC (112) is further adapted to provide analog control signals to input signal conditioning circuits (104, 106).

Signal conditioning circuit including a combined ADC/DAC, sensor system,

A circuit (34) for data recovery in a wireless powered communication device (10) obviates the need for the costly high power consumption filters of prior art devices by deriving a clock signal from the power coil (18), and then sampling the data coil (20) signal with the derived sampling clock. The step of deriving a clock signal from the power signal causes the component of the power signal present on the data signal to be aliased to DC which is then easily rejected with a low order high pass or bandpass filter (38). Furthermore, the data signal may be amplified to a desired level suitable for amplitude discrimination by a simple comparator circuit (40) with hysteresis. Demodulation of the data signal is easily accomplished in the digital domain using a digital demodulator (32).

Wireless powered communication device using power signal sampling and

The present invention expands the range over which a wireless powered communication device (500) and device reader (12) can communicate. In the present invention, circuitry (502) within the device (500) provides for determining a characteristic of the received communication signal. Based upon this signal characteristic data recovery parameters are adapted to enhance data recovery over a maximize communication distance. In a preferred embodiment of the present invention, the magnitude of the power signal is observed. It is known that the power signal varies as an inverse square of the distance of the device (500) to the reader. From this information, a data detection threshold is adjusted to enhance data recovery.

Wireless powered communication device with adaptive data detection and

An interference dependent adaptive phase clock controller method and system includes synthesis of a signal processing clock signal (307). An interference signal (311 ) dependent on a phase of the signal processing clock signal is measured, and a phase correction signal (317) is provided dependent thereon. A magnitude of the interference signal is reduced by adjusting the phase of the signal processing clock signal (307) dependent on the phase correction signal (317).

Interference dependent adaptive phase clock controller

A low voltage differential amplifier 10 or comparator is accomplished by providing an differential amplifier 10 that includes a transistor bias simulator 32 and a capacitance circuit 36. The transistor bias simulator 32 matches the gate to source bias voltage of the load transistor 22 and provides this value to the capacitance circuit 36. The capacitance circuit 36, which is coupled to a biasing reference voltage 38, charges a capacitor 84 based on the difference between the biasing reference voltage 38 and the simulated bias voltage 34. This charged capacitor 86 is used during an auto-zeroing phase to bias the drain to source voltage of the load transistor 22 to a state at which it is just beyond the onset of saturation.

Apparatus for a low voltage differential amplifier incorporating

A diagnostic system for measuring behavior of signals provided by a plurality of sensors (101, 129) includes a plurality of input filters (107, 135) for receiving signals (105, 133) from each of the plurality of sensors (103, 131) and for providing a plurality of filtered sensor signals (109, 137) each derived from the received signals (105, 133). A signal bandwidth of each of the plurality of filtered sensor signals (109, 137) is lower than a signal bandwidth of the than a signal bandwidth of the associated received signal. A selection circuit (119) receives each of the signals (105, 133) from each of the plurality of sensors (103, 131) and, dependent on a selection signal (127), provides a selected sensor signal (121) derived from one of the received signals (105), wherein the selected sensor signal (121) has a signal bandwidth greater than one of the filtered sensor signals (109) derived from the one of the received signals (105).

Growing community of inventors

Palatine, IL, United States of America

Neal W Hollenbeck