Nxp B.v.

Sonics, Incorporated

Synopsys, Inc.

St-Ericsson Sa

Neal Thomas Wingen

Gregory Ehmann

Drew Eric Wingard

Stephen W Hamilton

Niranjan Achugundla Puttaswamy

Tim Pontius

Greg Ehmann

Peter Klapproth

Swati Saxena

William John Bainbridge

An arbitrator governs an arbitration between different power domains and sequences powering up the different power domains supplied by the same voltage supply (VS) circuit on the Chip. The arbitrator has sequencing logic that limits how many different power domains simultaneously power up to a maximum amount, which is less than enough instantaneous electrical current drawn on the VS-circuit to cause a reduction below a minimum allowable supply voltage level for the VS-circuit. The sequencing logic manages the sequencing of powering up the different power domains by factoring in i) whether different power domains arbitrating to power up are part of a set of power domains that share the VS-circuit, ii) an amount of an instantaneous electrical current drawn, and iii) an amount of credits available before the minimum allowable supply voltage level occurs for that VS-circuit. The sequencing logic controls a behavior of the power domains when powering up from multiple different behaviors.

Power manager with a power switch arbitrator

Data payload is passed over a boundary from a sender module (SM) on one side of the boundary to a receiver module (RM) on the other side of the boundary. The SM has two or more multiplexers to pass the data payload over to a receiver storage register in the RM. Each multiplexer has 1) its own read address pointer lane coming from sequencing logic located on the RM side and 2) data slots to send data payload from that multiplexer across the boundary to the receiver storage register in the RM in a qualified event synchronization. The sequencing logic ensures that the multiple read address pointers going to the multiplexers have a fixed alternating relationship amongst themselves; and thus, the multiple read address pointers syncopate between each other to move the data payload across the boundary to provide 100% throughput.

Synchronizer with a timing closure enhancement

A data processing system comprises a plurality of sub-circuits, a clock generator provided with a control circuit, a pool of oscillator circuits comprising at least three oscillator circuits, and a multiplexing circuit coupled between the pool and clock inputs of the sub-circuits. The multiplexing circuit has a control input coupled to a control output of the control circuit. The multiplexing circuit is configured to couple any selectable one of the oscillator circuits in the pool to a clock input of each of the sub-circuits. The control circuit is configured to set the frequencies of respective ones of the clock circuit by controlling the multiplexing circuit to supply clock signals derived from selected ones of the oscillator circuits to the sub-circuits.

Clock generator

The invention relates to a controlled shut-down of an electronic circuit or circuits such that the electrical power consumption of that circuit or circuits is minimized and that each said circuit is at a status which is a pre-determined state () of that said circuit wherein all of its own control and messaging signals are taken to their zero level. The present invention claimed relates to the methodology of entering said circuit into this pre-determined state (); where all said signal and messaging lines are taken to zero; thereby reducing power consumption within an electronic circuit when its status is defined as being shut-down or standby.

Power management for buses in cmos circuits

When communicating data between different voltage and frequency domains, for example chiplets, in an integrated circuit, the data signals can be formatted to compensate for propagation delays and different operating frequencies between the domains, and the signaling voltage level of the formatted data signals can then be changed from the operating voltage of the transmitting domain to the operating voltage of the receiving domain so that the formatted and changed data signals can be transmitted. As such, voltage crossings are combined with frequency crossings, which can have the effect of hiding the voltage shifting within the propagation delays.

Circuits and methods for communicating data between domains during voltage and frequency shifting

A testing approach involves selective application of clock signals to target circuitry. In an example embodiment (), a target circuit () having logic circuitry that processes data in response to an operational clock signal () having at least one clock period, is analyzed for delay faults. Test signals are applied to the logic circuitry while the logic circuitry is clocked with a high-speed test clock () having several clock-state transitions that occur during at least one clock period of the operational clock (). An output from the logic circuitry is analyzed for its state (e.g., as affected by delay in the circuitry). Delay faults are detected as a difference in state of the output of the logic circuitry. With this approach, circuits are tested using conventional testers () that operate at normal (e.g., slow) speeds while selectively clocking selected portions of the circuit at higher speeds for detecting speed-related faults therein.

Growing community of inventors

Inverness, IL, United States of America

Neal Thomas Wingen