Lsi Logic Corporation

Mips Technologies, Inc.

Alcatel USA Sourcing, L.p.

Neal S Stollon

Thomas McCaughey

Bjorn Sihlbom

Dwight W Doss

Ernest Lewis Edgar

Jose A Garcia

Jairo A Afanador

An embedded system or system on chip (SoC) includes a secure JTAG system and method to provide secure on-chip control, capture, and export of on chip information in an embedded environment to a probe. In one embodiment, the system comprises encryption logic associated with a JTAG subsystem and decryption logic in the probe for encrypted JTAG read traffic. Inverted encryption/decryption logic provides bi-directional encryption and decryption of JTAG traffic. Encrypted information includes both authentication of valid probe/target interface and encryption of debug data.

System debug and trace system and method, and applications thereof

A heterogeneous integrated circuit having a digital signal processor and at least one programmable logic core. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. Memory sharing is controlled to allocate the full bandwidth of the DSP memory to the PLCs and other DMA devices in proportion to their operating speeds. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers.

DMA port sharing bandwidth balancing logic

A heterogeneous integrated circuit having a digital signal processor and at least one programmable logic core. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers.

DSP integrated with programmable logic based accelerators

A heterogeneous integrated circuit having a digital signal processor and two programmable logic cores, PLCs. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers. The DSP may reconfigure one PLC using the AMBA AHB, while it is processing data with the other PLC.

Heterogeneous integrated circuit with reconfigurable logic cores

A method of verifying transport within a delivery unit that interfaces telecommunications media to a switching matrix. Each channel of network data has an associated path verification code. The channels are transported within the delivery unit in subframes. For each channel, the path verification codes as well as a framing pattern are transported by accumulating path verification bits over a superframe. Path verification monitoring is performed regardless of channel position in the subframe and regardless of whether channels are in phase with each other.

Growing community of inventors

Dallas, TX, United States of America

Neal S Stollon