Intel Corporation

Micron Technology Incorporated

Neal R Mielke

Krishna Kumar Parat

Pranav Kalavade

Albert Fazio

Amit A Merchant

Gregory E Atwood

Steven E Wells

Krishna Seshan

Mickey L Fandrich

Paul D Ruby

Shantanu R Rajwade

Shyam Sunder Raghunathan

Xin Guo

Glen N Wada

Rex Stone

Kiran Pangal

Kerry Dean Tedrow

Mase J Taub

Yogesh B Wakchaure

Anand S Ramalingam

David J Pelster

Ye Zhang

Shirish Dnyaneshware Bahirat

Owen W Jungroth

Jerry G Jex

Hanmant Pramod Belgal

Branislav Vajdic

Sai Krishna Mylavarapu

Satoru Tamada

Iwen Chao

Alan E Baker

Mark Anthony Golez

Stephen F Sullivan

Eric Hoffman

Cole Uhlman

Mohammad Nasim Imtiaz Khan

Hoon Cho

Glen Wada

An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, maintain respective read disturb (RD) counters for each of two or more tracked units at respective granularities, maintain respective global RD counters for each of the two or more tracked units and, in response to a read request, increment one or more global RD counters that correspond to the read request, determine if a global RD counter for a tracked unit matches a random number associated with the tracked unit and, if so determined, increment a RD counter for the tracked unit that corresponds to the read request and generate a new random number for the tracked unit. Other embodiments are disclosed and claimed.

Read disturb tracking based on statistical probability

The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

Ramping inhibit voltage during memory programming

Methods and apparatus related to a mechanism for quickly adapting garbage collection resource allocation for an incoming I/O (Input/Output) workload are described. In one embodiment, non-volatile memory stores data corresponding to a first workload and a second workload. Allocation of one or more resources in the non-volatile memory is determined based at least in part on a determination of an average validity of one or more blocks, where the one or more candidate bands are to be processed during operation of the first workload or the second workload. Other embodiments are also disclosed and claimed.

Mechanism to adapt garbage collection resource allocation in a solid state drive

Described herein are an apparatus, system, and method for refreshing a non-volatile memory. The method comprises loading a time stamp, corresponding to data in a data location of a non-volatile memory, to a register; determining an elapsed time, corresponding to the data in the data location, according to the loaded time stamp; and refreshing data of the data location for which it is determined that the elapsed time exceeds a refresh time associated with the non-volatile memory.

Apparatus, system, and method for refreshing non-volatile memory

Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.

Memory devices and methods of storing data on a memory device

A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program/Erase cycling degradation of the single-level or multi-level cells of the flash memory module.

Method and apparatus for improving endurance of flash memories

A method and device using bitline-bitline capacitance between adjacent bitlines to boost seed voltage in a memory device are provided. The method may include a precharge phase, a boost phase, an equalize phase, and a lock in phase. In one embodiment, the method may include boosting the seed voltage twice. The bitlines may be divided into one or more segments.

Boosting seed voltage for a memory device

A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.

Integrated memory cell and method of fabrication

An integrated circuit is provided. The integrated circuit includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer includes a terminal dielectric layer. The integrated circuit further includes a planar passivating layer formed upon the terminal dielectric layer.

Planar guard ring

The present invention provides in one embodiment thereof an integrated circuit (IC) that includes silicon substrate. The integrated circuit includes a plurality of dielectric and metal layers formed upon the silicon substrate. The plurality of dielectric and metal layers form a die active area. The metal have formed therein a first guard wall surrounding the die active area. The metal layers further have formed therein a second segmented guard wall. The segmented guard wall surrounds and staples the plurality of metal layers. The IC also includes a passivation layer adhering to the first and the segmented guard walls.

Metal staples to prevent interlayer delamination

Growing community of inventors

Los Altos Hills, CA, United States of America

Neal R Mielke