Cirrus Logic Inc.

Data Systems Technology Corp.

Storage Technology Corporation

Other

Apple Inc.

Broadcom Corporation

Storage Technology Corporation Partners II

Reference Technology

Lake Cherokee Hard Drive Technologies, LLC

Neal Glover

Trent O Dudley

Richard T Behrens

Alan J Armstrong

Christopher P Zook

Larry D King

Kent D Anderson

Bill R Foland

John J Schadegg

William L Witt

David R Welland

William R Foland, Jr

Howard H Sheerin

John J Schadegg, Jr

William G Bliss

Paul M Romano

Richard Charles Williams

Kenneth R Burns

Hossein F Sevvom

Chris Mayne

Michael J O'Keeffe

Richard N Woolley

S Robert Perera

Dennis L Baker

David R Hieb

Peter Murray

Laura Droege Shellhamer

Randy Glissmann

Kermit Clausen

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

Synchronous read channel

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating analog as well as digital functions of the read channel in a single integrated circuit, and embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

A magnetic disk storage device employing an on-the-fly, multiple burst error correction system for detecting and correcting errors in data sectors stored on a magnetic disk, wherein each data sector comprises a data field and multiple sync marks for synchronizing to the data field. Multiple sync marks improve the probability of successful byte synchronization to the data field in the presence of noise in the system, such as defects in the storage medium. Further, a sync mark may be embedded within the data field to facilitate byte resynchronization when synchronization is lost.

Error correction method and apparatus

A cost reduced finite field processor is disclosed for computing the logarithm LOG.sub..alpha. (.alpha..sup.j) of an element of a finite field GF(2.sup.n) using significantly less circuitry than that required by a lookup table typically employed in the prior art. The result of the logarithm (i.e., the exponent of .alpha..sup.j) is represented as a binary number computed serially one bit per clock cycle. In one embodiment, combinatorial logic is used to compute bit 0 of the exponent. On each clock cycle, the exponent is shifted once to the right and bit of the exponent is extracted until the entire exponent has been computed. Shifting the exponent of a field element to the right is carried out by taking the square root of the element. The present invention requires at most n+1 clock cycles to compute LOG.sub..alpha. (.alpha..sup.j), with one embodiment requiring n/2 clock cycles. The circuitry for computing the square root of a field element and for computing bit 0 of the logarithm of a field element is significantly less than that required to implement the logarithm operation using a lookup table.

Cost reduced finite field processor for error correction in computer

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. Discrete time timing recovery within the read channel comprises a variable frequency oscillator (VFO) for generating a sampling clock. A center operating frequency of the VFO is adjusted through a programmable register which stores a digital center frequency setting. A phase error is computed from the sample values and combined with the center frequency setting to control the frequency and phase of the sampling clock at the output of the VFO.

Synchronous read channel employing a digital center frequency setting

A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlation data, confidence metrics from a sequence detector, and cross-correlation of expected sample errors with actual sample errors.

Channel quality circuit employing a test pattern generator in a sampled

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, computes a DC offset in the sample values in real time, and subtracts the DC offset from the read signal. This attenuates the deleterious affect a DC offset has on the detection algorithm used to detect the recorded data, such as the Viterbi detection algorithm.

Sychronous read channel

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. A Channel Quality circuit accumulates various signals generated by the read channel, such as sample errors, gain errors, timing errors, etc., for use in calibrating the read channel components and estimating the bit error rate.

Synchronous read channel integrated circuit employing a channel quality

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a partial response of the form (1-D)(1+D).sup.n where n&gt;1, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector.

Synchronous read channel integrated circuit employing discrete time

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.

Synchronous read channel employing a frequency synthesizer for locking a

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. The read channel further employs an error tolerant sync mark detector, as well as a sync mark recovery procedure for synchronizing to the data when the sync mark is destroyed by a defect.

Synchronous read channel sintegrated circuit employing a fault tolerant

A magnetic disc storage system employing two stage actuators for simultaneously positioning recording heads over the top and bottom surfaces of the disc is disclosed. The recording heads are fastened to a distal end of respective top and bottom load beams. A base end of the load beams is connected to a voice coil motor (VCM) rotary actuator which simultaneously positions both recording heads over the disc. A silicon microactuator is also fastened to the distal end of at least one of the load beams for positioning the recording heads independent of one another, thereby allowing simultaneous tracking of embedded servo data. Various data formats are provided, including interleaving logical sector numbers, symbols of a logical sector, and segments of a logical sector, between the top and bottom physical sectors of a track. Complexity and cost of the servo controllers is reduced through the use of sliding mode control: a simple, robust and fast control system implemented using simple switching circuitry, small lookup tables, and simplified binary multipliers (shift registers). A dual path read channel implemented in a single integrated circuit is provided for parallel processing the read signals from the top and bottom recording heads.

Magnetic disc recording system employing two stage actuators for

Apparatus and methods are disclosed for providing an improved system for encoding and decoding of Reed-Solomon and related codes. The system employs a k-bit-serial shift register for encoding and residue generation. For decoding, a residue is generated as data is read. Single-burst errors are corrected in real time by a k-bit-serial burst trapping decoder that operates on this residue. Error cases greater than a single burst are corrected with a non-real-time firmware decoder, which retrieves the residue and converts it to a remainder, then converts the remainder to syndromes, and then attempts to compute error locations and values from the syndromes. In the preferred embodiment, a new low-order first, k-bit-serial, finite-field constant multiplier is employed within the burst trapping circuit. Also, code symbol sizes are supported that need not equal the information byte size. The implementor of the methods disclosed may choose time-efficient or space-efficient firmware for multiple-burst correction.

Reed-Solomon code system employing k-bit serial techniques for encoding

A disc drive storage system having a plurality of data tracks and data sectors within each track, wherein each track further comprises a redundancy sector for reconstructing a data sector unrecoverable at the sector level. The latency of the storage system is minimized by generating track level redundancy data over the write range of data sectors and storing the 'write' redundancy to the redundancy sector. Then during idle time of the storage system, the track level redundancy is regenerated for the entire track. If an unrecoverable data sector is encountered during the idle time redundancy regeneration, and the unrecoverable data sector is within the write range of the previous write operation, then it is reconstructed using the track level redundancy data stored in the redundancy sector.

Write verify method for correcting unrecoverable sectors in a disc

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To increase the throughput of the read channel, multiple sample values are processed in parallel. In the example embodiment disclosed herein, two sample values are processed in parallel.

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Broomfield, CO, United States of America

Neal Glover