Spin Memory, Inc.

Crocus Technology Inc.

Zeno Semiconductor, Inc.

Crocus-technology Sa

Integrated Silicon Solution, (cayman) Inc.

Spin Transfer Technologies, Inc.

Atmel Corporation

Silicon Storage Technology, Inc.

Integrated Silicon Solution Incorporated

Neal Berger

Benjamin S Louie

Lester Crudele

Mourad El Baraji

Mourad El-Baraji

Daniel L Hillman

Susmita Karmakar

Yuniarto Widjaja

Jin-Woo Han

Kuk-Hwan Kim

TaeJin Pyon

Virgile Javerliac

Geoffrey S Gongwer

Barry Hoberman

Bertrand Francis Cambou

Amitay Levi

Jean-Pierre Nozieres

Pearl Po-Yee Cheng

Ben Louie

Jean-Pierre Nozières

James Fahey

Srinivas Ramamurthy

George Chia-Jung Chang

Kadriye Deniz Bozdag

Lucien Lombard

Lester M Crudele

Anne Pao-Ling Koh

Keith H Gudger

Guillaume Prenat

Kenneth Donald Mackay

Jinglun Eugene Tam

Eugene Jinglun Tam

Joe Yu

Wendey E Mueller

James C Khong

William Saiki

Ricardo Alves Ferreira Costa E Sousa

William J Saiki

Benjamin Stanley Louie

Kenneth Mackay

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

Memory device comprising electrically floating body transistor

Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.

MRAM access coordination systems and methods via pipeline in parallel

A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.

Error cache system with coarse and fine segments for power optimization

A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.

Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments

A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.

Word line decoder memory architecture

A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells and a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank. The memory also comprises a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, and wherein a write verification operation associated with a data word of the second plurality of data words is performed a predetermined period of time after the data word is written into the memory.

Circuit engine for managing memory meta-stability

MRAM access coordination systems and methods with a plurality of pipelines

A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Also, the cache memory is divided into a plurality of segments, wherein each segment of the cache memory is direct mapped to a corresponding segment of the memory bank, wherein an address of each of the second plurality of data words is mapped to a corresponding segment in the cache memory, and wherein data words from a particular segment of the memory bank only get stored in a corresponding direct mapped segment of the cache memory.

Error cache segmentation for power reduction

A method of writing data into a memory device comprising utilizing a pipeline to process write operations of a first plurality of data words addressed to a plurality of memory banks, wherein each of the plurality of memory banks is associated with a counter. The method also comprises writing a second plurality of data words and associated memory addresses into an error buffer, wherein the error buffer is associated with the plurality of memory banks and wherein further each data word of the second plurality of data words is either awaiting write verification associated with a bank from the plurality of memory banks or is to be re-written into a bank from the plurality of memory banks. Further, the method comprises maintaining a count in each of the plurality of counters for a respective number of entries in the error buffer corresponding to a respective memory bank.

Determining an inactive memory bank during an idle memory cycle to prevent error cache overflow

A method of writing data utilizes a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method also comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification. Additionally, the method comprises searching for at least one data word that is awaiting write verification in the error buffer, wherein verify operations associated with the at least one data word occur in a same row as the write operation. Finally, the method comprises determining if an address associated with any of the at least one data word is proximal to an address for the write operation and preventing a verify operation associated with the at least one data word from occurring in a same cycle as the write operation.

MRAM noise mitigation for write operations with simultaneous background operations

A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank and writing a second plurality of data words and associated memory addresses into an error buffer. The method also comprises monitoring a first counter value which tracks a number of write 1 errors and a second counter value which tracks a number of write 0 errors in the memory bank. Further, the method comprises determining if the first counter value and the second counter value have exceeded a predetermined threshold. Responsive to a determination that the first counter value has exceeded the predetermined threshold increasing a write 1 voltage of the memory bank, and, further, responsive to a determination that the second counter value has exceeded the predetermined threshold increasing a write 0 voltage of the memory bank.

Bi-polar write scheme

Growing community of inventors

Cupertino, CA, United States of America

Neal Berger