Micron Technology Incorporated

Lexar Media, Inc.

Neal Anthony Galbo

Victor Y Tsai

William Henry Radke

Peter Sean Feeley

Robert N Leibowitz

James Cooke

Danilo Caraccio

Daniele Balluchi

Ngon Van Le

Robert Warren

Petro Estakhri

Berhanu Iman

Martin Ragnar Furuhjelm

Jerrold Allen Beckmann

Steffen Markus Hellmold

Jarreth Romero Solomon

Chad A Cobbley

Krishnam R Datla

Krishnam R Dalta

Danilo Carracio

The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Command queuing

The present disclosure includes apparatuses, methods, and systems for data relocation in memory. An embodiment includes a controller, and a memory having a plurality of physical units of memory cells. Each of the physical units has a different sequential physical address associated therewith, a first number of the physical units have data stored therein, a second number of the physical units do not have data stored therein, and the physical address associated with each respective one of the second number of physical units is a different consecutive physical address in the sequence. The controller can relocate the data stored in the physical unit of the first number of physical units, whose physical address in the sequence is immediately before the first of the consecutive physical addresses associated with the second number of physical units, to the last of the consecutive physical addresses associated with the second number of physical units.

Data relocation in memory

The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

State change in systems having devices coupled in a chained configuration

The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.

Packet deconstruction/reconstruction and link-control

The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.

Methods for controlling host memory access with memory devices and systems

The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Host controller

The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.

Boot partitions in memory devices and systems

Growing community of inventors

Boca Raton, FL, United States of America

Neal Anthony Galbo