Intel Corporation

Nazar Syed Haider

Ankush Varma

Dean A Mulla

Adwait Purandare

Srinivasan Rajagopalan

Aman Sewani

Donald C Soltis, Jr

Krishnakanth Venkata Sistla

Andrew J Herdrich

Yen-Cheng Liu

Alexander Gendler

Vivek Garg

Bahaa Fahim

Nikhil Gupta

Bongjin Jung

Ariel Szapiro

Tejpal Singh

Ripan Das

Cau L Nguyen

Yogesh Bansal

Suresh Chemudupati

Eric Dehaemer

Nilanjan Palit

Allen W Chu

Chung-Chi Wang

Rupal Parikh

Amit Gabai

Daniela Kaufman

Ujjwal Gupta

Pavithra Sampath

Stanley Chen

Terry C Huang

Sooseok Oh

Nikethan Shivanand Baligar

Lan Vu

Stephen Wang

Dorit Shapira

Shruthi Venugopal

Phani Kumar Kandula

Michael Tulanowski

Gilad Bomstein

Shlomo Attias

Timothy Yee-Kwong Kam

Stephen Paul Haake

Hendra Rustam

Guneet Singh

An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (P0nMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.

Apparatus and method to detect power supply security attack and risk mitigation

A scheme is provided for a processor to measure or estimate the dynamic capacitance (Cdyn) associated with an executing application and take a proportional throttling action. Proportional throttling has significantly less impact on performance and hence presents an opportunity to get back the lost bins and proportionally clip power if it exceeds a specification threshold. The ability to infer a magnitude of power excursion of a power virus event (and hence, the real Cdyn) above a set power threshold limit enables the processor to proportionally adjust the processor operating frequency to bring it back under the limit. With this scheme, the processor distinguishes a small power excursion versus a large one and reacts proportionally, yielding better performance.

Real-time power meter for optimizing processor power management

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.

Shared mesh

Systems, methods, and devices are disclosed for mitigating voltage droop in a computing device. An example apparatus includes a plurality of threshold registers to store respective voltage droop thresholds, and an interface to receive a license grant message indicating a license mode for a processor core or domain. The license mode corresponds to a selected set of execution units in the processor core or domain. The apparatus also includes a voltage droop correction module to, based on the license mode indicated in the license grant message, select one of the voltage droop thresholds from the plurality of voltage droop registers, and compare a voltage droop in the processor core or domain with the selected voltage droop threshold. Based on the comparison, the apparatus triggers a voltage droop correction process.

Systems and methods for core droop mitigation based on license state

Methods and apparatus relating to techniques for mesh performance improvement using dual voltage data transfer are described. In one embodiment, a first plurality of signal paths are operated at a higher voltage level than a second plurality of signal paths. The first plurality of signal paths comprises Resistor-Capacitor (RC) dominated signal paths that move signals between any two system tiles. Other embodiments are also disclosed.

Mesh performance improvement using dual voltage data transfer

A circuit that enables a safe power-on sequencing is described. The circuit enables a processor to be powered by an internal or external voltage source. The circuit detects for the presence of an external voltage regulator. If an external voltage generator is not providing a valid voltage source to the processor, the circuit enables an internal voltage regulator to provide a stable voltage source.

Circuit for enabling dual mode safe power-on sequencing

A voltage reference generator for a hysteresis circuit, comprising a first originator circuit to generate a first reference voltage; a second originator circuit to generate a second reference voltage; and a selector circuit, coupled to the first and second originator circuits, to select one of the first and second reference voltages to be an output reference voltage based upon an input signal to the hysteresis circuit undertaking a low-to-high or a high-to-low signal transition respectively. The first originator circuit includes a first plurality of channel devices selected from either p-channel devices or n-channel devices and the second originator circuit includes a second plurality of channel devices selected from the other one of the p-channel devices and the n-channel devices.

Reference voltage generator for hysteresis circuit

A circuit for protecting internal logic circuits of an integrated circuit (IC) device from a failure of internal voltage supply is disclosed. A protection circuit is connected between the internal power supply and an external power supply. The protection circuit reduces the external power to the internal logic circuits. A pass circuit is connected to the protection circuit and the internal power supply. The pass circuit is configured to reduce the input voltage difference in the protection circuit in the event of a failure of the internal power supply to prevent a failure of the protection circuit. The voltage level of the external power supply is typically higher than the internal supply voltage level, and exposure to the full external voltage level may disable the protection circuit.

Circuit and method for protecting input/output stage of a low voltage integrated circuit device from a failure of the internal power supply or in the power-up sequencing of power supplies

Briefly, in accordance with one embodiment of the invention, a slew rate control circuit for a processor includes: a circuit configuration to produce a signal representing the speed of fabricated transistors; and a circuit configuration to adjust, based at least in part on the signal representing the speed of fabricated transistors, the amount of current produced by a pre-driver stage for an output buffer of the processor. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a slew rate control circuit for a buffer including: a register capable of storing at least one binary digital signal, a pre-driver, and at least one pre-driver cell coupled to the pre-driver. The at least one pre-driver cell is coupled to the pre-driver and register so as to modify the amount of current produced by the pre-driver based, at least in part, on the at least one binary digital signal.

Slew rate control circuit

A circuit for driving GTL-type buses actively drives a bus trace towards a first reference voltage when a signal in a first voltage state is detected at its input and actively drives the bus trace towards a second reference voltage for a selected period when the signal at its input transitions from the first voltage state to a second voltage state. The circuit includes a flip-flop for storing the sequential voltage states of the signal, logic for comparing the current voltage state of the signal with a replica of the preceding voltage state of the signal, and first and second transistors of complementary conductivity types, for driving the bus trace to first or second reference voltages, respectively, when activated. The first transistor is turned on when the signal is in the first voltage state. The second transistor is turned on for a period determined by the clock signal driving the flip flop, the type of flip-flop, and, optionally, additional logic gates, when the signal transitions from the first voltage state to the second voltage state.

Timed one-shot active termination device

Circuit for protecting the input/output stage of a low voltage

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Fremont, CA, United States of America

Nazar Syed Haider