Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Other

Naysen J Robertson

Sachin Navin Chheda

Theodore F Emerson

Benjamin Thomas Percer

David F Heinrich

Ricardo Ernesto Espinoza-Ibarra

Robert L Noonan

Christopher M Wesneski

Kenneth T Chin

William J Walker

Luis E Luciani, Jr

Sai Rahul Chalamalasetti

Shiva R Dasari

Kevin Edward Boyum

Stephen B Lyle

Kirk Yates

Akbar Monfared

Robert D Odineal

Gennadiy Rozenberg

Nitin C Bhagwath

Jhovel Louie Lopez

Dave W Paulson

Samuel Gonzalez

Robert N Barry

An apparatus includes a host and a baseboard management controller. The baseboard management controller includes a semiconductor package; and the semiconductor package includes a memory, a security hardware processor; and a main hardware processor. The main hardware processor causes the baseboard management controller to serve as an agent that, independently from the host, responds to communications with a remote management entity to manage the host. The security hardware processor manages the storage of a secret of the host in the memory.

Managing storage of secrets in memories of baseboard management controllers

In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.

Configuration of configurable test logic

In some examples, an apparatus includes a management controller for use in a computer system having a processing resource for executing an operating system (OS) of the computer system, the management controller being separate from the processing resource and to perform, based on operation of the management controller within a cryptographic boundary, management of components of the computer system, the management of components comprising power control of the computer system. The management controller is to receive sensor data, perform facial recognition based on the sensor data, and determine whether to initiate a security action responsive to the facial recognition.

Facial recognition based security by a management controller

A data processing system comprises a management processor, a programmable logic device (PLD) coupled to the management processor, and a machine-readable medium (MRM). The MRM comprises a PLD configuration image to configure the PLD with image-defined logic that comprises self-verification logic and an image-defined management interface to enable the management processor to communicate with the self-verification logic. The MRM also comprises a cryptographic signature based on the PLD configuration image. The MR also comprises PLD authentication instructions which, when executed by the management processor, cause the management processor to retrieve an address for the PLD configuration image from the PLD via the management interface, use the address to retrieve the PLD configuration image from the PLD via the management interface, retrieve the cryptographic signature from the PLD via the management interface, and use the cryptographic signature and a cryptographic key of a trusted entity to authenticate the PLD configuration image.

Verification of programmable logic devices

An apparatus includes a subsystem, a first processor, a memory, a circuit and a second processor. The first processor is to execute bootstrap instructions, and the memory is to store second instructions. The circuit is to hold the first processor in reset in response to the apparatus being powered on; and the second processor is to, while the first processor is held in reset, execute the second instructions to initialize the subsystem.

Processors to configure subsystems while other processors are held in reset

A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.

Directing control data between semiconductor packages

An apparatus includes a plurality of subsystems, including a first subsystem and a second subsystem. The apparatus includes a master processor to, in response to a power on of the apparatus, execute first instructions to configure the first subsystem and provide second instructions. The apparatus further includes a slave processor to, prior to the boot of the apparatus, receive the second instructions from the master processor and execute the second instructions to configure the second subsystem.

Configuring first subsystem with a master processor and a second subsystem with a slave processor

A system includes a first physical chassis comprising a first chassis management unit ('CMU'). The first CMU is configured to communicate with a second CMU in an additional physical chassis. The first CMU is also configured to communicate for the first physical chassis and the additional physical chassis as one logical chassis.

Physical chassis as a different number of logical chassis

The present invention provides a margin testing system, incorporated in an electronic system (e.g., a computer system), that includes a controller, a frequency control module, and a voltage control module, and a fault bypass module. In response to commands from the controller, the frequency control module and/or the voltage control module can set a test clock frequency and/or a test voltage for application to one or more components of the electronic system to elicit system response to these test values. The response of the system at each test value can be monitored, e.g., by executing a diagnostics software, and analyzed. The fault bypass module can mask fault signals during margin testing to ensure that these signals will not disrupt margin testing of the system.

Method and construct for enabling programmable, integrated system margin testing

The present invention provides systems and methods for performing frequency margin testing of a computer system, such as a server. A system of the invention can include a controller, e.g., a BMC, internal to the computer system and a digital frequency synthesizer that can communicate with the controller and can apply clock frequency to marginable components of the computer system. In response to commands from the controller, the synthesizer generates one or more test frequencies that are applied to one or more of the marginable components. The response of the system to each of the test frequencies is then monitored.

Use of I2C programmable clock generator to enable frequency variation under BMC control

The present invention provides a voltage margin testing system incorporated in an electronic system, such as, a computer system (e.g., a server), having a plurality of components for at least some of which voltage margin testing is required. A voltage margin testing of the invention can include a controller, such as a Baseboard Management Controller (BMC), internal to the computer system and a digital voltage adjuster, e.g., a digital potentiometer, that is in communication with the controller. The voltage adjuster can effect generation of one or more test voltages, for example, by varying resistance in a feedback circuitry of a regulator whose output voltage is applied to system components, for application to the components in response to commands from the controller.

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In one embodiment, the invention recites a fan motor assembly with integrated redundant availability. The fan motor assembly comprises a fan motor subassembly with a plurality of replaceable fan motors, and a fan motor selector mechanism coupled to the fan motor subassembly, so that the fan motor selector mechanism selectively engages one of the plurality of replaceable fan motors to a fan. The fan motor assembly further comprises a control unit which is coupled to the fan motor selector mechanism which is configured to control the fan motor selector mechanism such that a first replaceable fan motor mechanically powers the fan while a second replaceable fan motor can be dynamically removed from the fan motor subassembly.

Scalable, modular, high availability fan system

A fan controller in one exemplary embodiment facilitates control over a cooling system having fans in a computing apparatus, and permits operating system and application program based software inputs as well as hardware inputs to be utilized in the control of the fans.

Multifunctional control of cooling systems for computers

A fan motor assembly with integrated redundant availability is recited. The fan motor assembly can include a fan motor subassembly with a first fan motor and a second fan motor, and a fan motor selector mechanism coupled to the fan motor subassembly, so that the fan motor selector mechanism selectively couples the first fan motor or second fan motor to a fan. The fan motor assembly can also include a control unit coupled to the fan motor selector mechanism, wherein the control unit is configured to control the fan motor selector mechanism such that either of the first fan motor and second fan motor is selectively engaged to the fan.

Growing community of inventors

Orangevale, CA, United States of America

Naysen J Robertson