Intel Corporation

Nayan Amrutlal Suthar

David M Puffer

Michael D Ruehle

Robert J McMillen

Todd M Rimmer

Rahul Pal

Ajaya V Durg

Mark Debbage

Sayantan Sur

Bruce G Warren

Ashok Jagannathan

Vinay Janardan Naik

Umesh Ramkrishnarao Kasture

A processor unit comprising a first controller to couple to a host processing unit over a first link; a second controller to couple to a second processor unit over a second link, wherein the second processor unit is to couple to the host central processing unit via a third link; and circuitry to determine whether to send a cache coherent request to the host central processing unit over the first link or over the second link via the second processing unit.

Peer-to-peer link sharing for upstream communications from XPUS to a host processor

Examples described herein relate to a first graphics processing unit (GPU) with at least one integrated communications system, wherein the at least one integrated communications system is to apply a reliability protocol to communicate with a second at least one integrated communications system associated with a second GPU to copy data from a first memory region to a second memory region and wherein the first memory region is associated with the first GPU and the second memory region is associated with the second GPU.

Direct memory writes by network interface of a graphics processing unit

Disclosed is an architecture, system and method for performing multi-thread DFA descents on a single input stream. An executer performs DFA transitions from a plurality of threads each starting at a different point in an input stream. A plurality of executers may operate in parallel to each other and a plurality of thread contexts operate concurrently within each executer to maintain the context of each thread which is state transitioning. A scheduler in each executer arbitrates instructions for the thread into an at least one pipeline where the instructions are executed. Tokens may be output from each of the plurality of executers to a token processor which sorts and filters the tokens into dispatch order.

Multithreaded DFA architecture for finding rules match by concurrently performing at varying input stream positions and sorting result tokens

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Maharashtra, India

Nayan Amrutlal Suthar