Lsi Corporation

Agere Systems Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Agere-010200us

Avago Technologies International Sales Pte. Limited

Nayak Ratnakar Aravind

Haitao Xia

Scott M Dziak

Erich Franz Haratsch

Richard Rauschmayer

James Arthur Bailey

Lu Pan, Sr

Bruce Alexander Wilson

Weijun Tan

Yu Liao

Robert H Leonowich

Haotian Zhang

Yang Cao

George Mathew

Suharli Tedja

Systems and methods are disclosed relating generally to data processing, and more particularly to applying low pass and rotation filtering in relation to data processing. For example, a system may include a phase modification value determination circuit operable to generate a phase offset value based upon an input data set derived from information sensed from a storage medium. The system may include an integrated low pass and rotation filtering circuit operable to simultaneously apply a low pass filtering function and phase rotation function to a series of digital samples derived from the information sensed from the storage medium to yield a modified output. Application of both the low pass filtering and phase rotation functions is governed at least in part based upon a selected coefficient set corresponding to a combination of the phase off set value and a boost value.

Systems and methods for a data processing using integrated filter circuit

Systems and methods relating generally to data processing, and more particularly to adjusting gain parameters in relation to data processing.

Systems and methods for acquisition phase gain modification

Systems and methods for magnetoresistive asymmetry estimation may include, but are not limited to, operations for: receiving a magnetic read head transducer output; computing a mean value of the magnetic read head transducer output; computing a median value of the magnetic read head transducer output; and applying a correction coefficient to a magnetic read head detector input according to at least the mean value of the magnetic read head transducer output and the median value of the magnetic read head transducer output.

Non-decision directed magnetoresistive asymetry estimation

A magnetic recording system includes an array of analog inputs operable to receive an array of analog signals retrieved from a magnetic storage medium, where one of the array of analog signals corresponds with a reference channel, a timing recovery circuit operable to generate a clock signal based on the analog signal for the reference channel, a number of analog to digital converters each operable to sample one of the array of analog signals based on the clock signal to yield a number of digital channels, and a joint equalizer operable to filter the digital channels to yield an equalized output.

Array-reader based magnetic recording systems with mixed synchronization

Systems and method relating generally to data processing, and more particularly to systems and methods for tone reduction in relation to data transmission. In one case, a data processing system is disclosed that includes: a two stage tone reduction circuit including a first stage circuit and a second stage circuit; and a polarity change circuit operable to change a polarity of the second stage output to yield a tone reduction output.

Systems and methods for two stage tone reduction

Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Systems and methods for low latency media defect detection

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, and a magneto-resistive adjustment circuit. The analog to digital converter circuit is operable to convert an input signal into corresponding digital samples. The magneto-resistive adjustment circuit is operable to reduce signal asymmetry in the digital samples due to sensing by a magneto-resistive head to yield a corrected output.

Systems and methods for digital MRA compensation

Methods and apparatus are provided for determining coefficients for a digital low pass filter, given cutoff and boost values for a corresponding analog version of the digital low pass filter. Coefficients are determined for a digital low pass filter by obtaining cutoff and boost values for a corresponding analog version of the digital low pass filter; and determining the coefficients for the digital low pass filter based on the obtained cutoff and boost values. The coefficients can be determined, for example, by generating a transfer function, H(s), for the corresponding analog version using the obtained cutoff and boost values: transforming the transfer function, H(s), to a frequency domain characterization, H(z), using one or more bilinear transforms to obtain a plurality of coefficients for an infinite impulse response (IIR) filter; generating the IIR filter using the plurality of coefficients for the IIR filter; and applying an impulse to the IIR filter to obtain the one or more coefficients for the digital low pass filter. In another variation, the coefficients are pre-computed and obtained from a look-up table.

Determining coefficients for digital low pass filter given cutoff and boost values for corresponding analog version

Various embodiments of the present invention provide systems, methods and media formats for efficiently determining a position error of a head in relation to a storage medium. In one case, a system is disclosed that includes a storage medium with a series of data. The series of data includes a first defined marker and a second defined marker located a distance from the first defined marker, and position location data. The systems further include a first detector circuit that is operable to detect the first defined marker and to establish a location of the first defined marker, and a second detector circuit that is operable to detect the second defined marker and to establish a location of the second defined marker. The systems further include an error calculation circuit and an interpolation circuit. The error calculation circuit is operable to calculate an interpolation offset based at least in part on the location of the first defined marker and the location of the second defined marker. The interpolation circuit is operable to interpolate the position location data and to provide an interpolated position location data.

Systems and methods for improved servo data operation

Methods and apparatus are provided for processing a signal in a read channel using a selective oversampled analog to digital conversion. The disclosed selective oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain. An analog input signal in a read channel is converted to a digital signal to generate one or more digital samples corresponding to the analog input signal for a given bit interval. The analog input signal is selectively filtered in an analog domain in a first mode and the digital samples are selectively filtered in a digital domain in a second mode. A data detection algorithm is applied to the digital samples to obtain a detected output. The selection of the first mode and the second mode can be, for example, based on channel conditions. The analog to digital conversion can be performed at a baud rate in the first mode and at an oversampled rate in the second mode.

Read channel with selective oversampled analog to digital conversion

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes: a data detector circuit, a low latency detection circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output, and to provide a loop error as a difference between the detected output and the first signal. The low latency detection circuit operable to process a second signal derived from the data input to yield a fast detector output, and to provide a generated error as a difference between the fast detector output and the second signal. The error calculation circuit is operable to calculate an error value based at least in part on the generated error and the loop error.

Systems and methods for reduced latency loop correction

Various embodiments of the present invention provide apparatuses and methods for processing data in an oversampled data processing circuit with multiple detectors. For example, an apparatus for processing data is disclosed that includes a first analog to digital converter operable to sample a continuous signal at a first sampling phase to yield a first digital output, a second analog to digital converter operable to sample the continuous signal at a second sampling phase to yield a second digital output, wherein the second sampling phase is different from the first sampling phase, a first detector operable to process the first digital output to yield a first detector output, and a second detector operable to process the second digital output and the first detector output to yield a detected output.

Oversampled data processing circuit with multiple detectors

Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, some embodiments provide data processing circuits that include: an input circuit, a processing circuit, a data detection circuit, and a baseline compensation circuit. The input circuit receives a first data input and provides a second data input. The input circuit excludes low frequency energy exhibited in the first data input from the second data input. The processing circuit generates a representation of the second data input, and the data detection circuit generates a representation of the first data input based at least in part on the representation of the second data input. The baseline compensation circuit calculates an accumulated difference between the representation of the first data input and the representation of the second data input across a number of bit periods, and calculates a compensation factor based at least in part on the accumulated difference.

Systems and methods for adaptive baseline compensation

Methods and apparatus are provided for processing a signal in a read channel using an oversampled analog to digital conversion. An oversampled analog to digital conversion is performed on an analog input signal to generate a plurality of digital samples corresponding to the analog input signal for a given bit interval. A data detection algorithm can then be applied on one or more of the digital samples to obtain a detected output. The oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain.

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Allentown, PA, United States of America

Nayak Ratnakar Aravind