Silicon Graphics, Incorporated

Nawaf K Bitar

Robert M English

Rajagopal Ananthanarayanan

Alexander D Petruncola

David Craig

A system and a method of scheduling a plurality of threads from a multi-threaded program. A shared arena is provided in user memory, wherein the shared arena includes a register save area for each of the plurality of threads. A processor, when allocated to the application, executes the application's user-level scheduler and selects a user-level thread from a plurality of available threads, wherein the step of selecting includes the step of reading register context associated with the selected thread from one of the plurality of register save areas. In multikernel systems, kernels having access to an application's register save areas can execute preempted threads from that application with no kernel-to-kernel communication. Likewise, kernels having access to an application's user-level run queues can execute ready-to-run threads from that application with no kernel-to-kernel communication.

Distributed scheduling of parallel jobs with no kernel-to-kernel communication

A precise earnings-based time-share scheduler schedules multiple jobs in a computer system by apportioning earnings, at scheduler ticks. Earnings are apportioned to jobs based on actual time a job spent in a queue requesting execution on a central processing unit (CPU) in the computer system between scheduler ticks and amounts of time jobs ran on the CPU between scheduler ticks. At the end of a time slice, a job is selected for execution on the processor based on earnings apportioned to each job.

Earnings-based time-share scheduling

A system and method for inexpensively detecting preempted execution entities such as threads without kernel involvement. In a computer system having a memory and one or more processors, a shared memory arena is formed in user space within the memory. A preempt bit vector is then formed within the shared memory arena such that the preempt bit vector is accessible to any of a plurality of execution entities running in user mode. The preempt bit vector includes a plurality of rbits, wherein each rbit is associated with one of the plurality of execution entities and wherein an rbit is marked whenever its associated execution entity is preempted. Detection of preempted threads then becomes a matter of reading, via program code executing in user mode on one of the plurality of processors, bits in the preempt bit vector to detect preempted execution entities.

System and method for finding preempted threads in a multi-threaded application

A batch job scheduler facility schedules batch jobs in a general purpose multiprocessor system having resources, such as processors and memory, and running interactive and batch jobs. The resources are allocated to the batch jobs. Completion times are calculated and guaranteed for the batch jobs based on the resources allocated to the batch jobs. The completion times are calculated and guaranteed without static partitioning, resulting in improved utilization of system resources. Batch-critical batch jobs are defined which require all their allocated resources to complete by their guaranteed completion time. The batch jobs are scheduled so that batch jobs and interactive jobs compete for the same resources. Batch-critical jobs are permitted to obtain all their allocated resources.

Guaranteeing completion times for batch jobs without static partitioning

A low-latency real-time dispatching scheme performed by the operating system of a general purpose multiprocessor system having N processors, assigns a priority to each of multiple real-time threads to be executed on the N processors. The multiple real-time threads include up to N top priority real-time threads, which are bound to a corresponding processor. The assigned priority of each bound real-time thread is the highest priority for being executed on its corresponding processor, and any other real-time thread being executed on the corresponding processor is preempted if the bound real-time thread becomes runnable.

Low-latency real-time dispatching in general purpose multiprocessor

A system and method for context switching between a first and a second execution entity (such as a thread) without having to enter into protected kernel mode. The system includes a memory and a plurality of processors, wherein each of the plurality of processors operates within both a user mode and a protected kernel mode and includes a program counter and a plurality N of registers. The first and second execution entities have user states defined by a program counter value, a context identifier value and N register values. To switch context, an execution entity such as a thread, while in user mode, writes the user state of the first execution entity to memory. It then restores the user state of the second execution entity by writing register values associated with the second execution entity to all but a first register and writing the context identifier value to a context identifier location. The program counter value is then written to the first register and a jump performed to the program counter value stored in the first register while the last remaining register value is loaded to the first register. Each of these steps is performed in user mode; the result is an efficient way of switching from one user thread to the next user thread without entry into kernel space.

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San Jose, CA, United States of America

Nawaf K Bitar