Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Navneet Gupta

Adam Makosiej

Costin Anghel

Amara Amara

Olivier Thomas

Tri-state inverter includes a n-TFET and a p-TFET, the drain of the n-TFET being connected to the drain of the p-TFET and to an output of the tri-state inverter, the gates of the n-TFET and p-TFET being connected to an input of the tri-state inverter, and a control circuit able to apply a first control voltage on the source of the n-TFET and a second control voltage on the source of the p-TFET, the values of the first and second control voltages being positive or zero, wherein, when the tri-state inverter is intended to work as an inverter, the value of the first control voltage is lower than the value of the second control voltage, and when the tri-state inverter is intended to be tri-stated, the value of the first control voltage is higher than the value of the second control voltage.

Tri-state inverter, D latch and master-slave flip-flop comprising TFETs

A SRAM memory bit cell is provided that includes a n-TFET and a p-TFET; a storage node formed by the connection of a first electrode of the n-TFET to a first electrode of the p-TFET (drains or sources); and a control circuit able to apply supply voltages on second electrodes of the n-TFET and p-TFET (sources or drains). The control circuit is configured to provide, during a retention mode, supply and bias voltages reverse biasing the n-TFET and p-TFET in a state wherein a conduction current is obtained by band-to-band tunneling in the n-TFET and p TFET. The control circuit is further configured to provide, during a writing of a bit, supply and bias voltages forward biasing the n-TFET and p-TFET and such that one of the n-TFET and p-TFET is in OFF state and that the other of the n-TFET and p-TFET is in ON state.

SRAM memory bit cell comprising n-TFET and p-TFET

A content addressable memory having at least one CAM cell including first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bitline, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bitline, the second transistor being controlled by a second control signal; and a control circuit adapted to perform a CAM read operation by pre-charging the bitline to a first voltage level, and then selectively activating either the first or second transistor based on a bit of input data.

Growing community of inventors

Grenoble, France

Navneet Gupta