Micron Technology Incorporated

Micron Semiconductor, Inc.

Navjot Chhabra

Eric A Powell

Gurtej S Sandhu

Stephen R Porter

Rodney D Morgan

Loyal R Gibbons

The present invention discloses an on chip decoupling capacitor structure having a first decoupling capacitor with one electrode formed in the conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. The second electrode is a common electrode to a second decoupling capacitor overlying and thereby coupled in parallel to said first decoupling capacitor. The second capacitor's first electrode is the common electrode and its second electrode is made of conductively doped polysilicon. The electrodes made of the conductively doped polysilicon may be further enhanced by forming a silicided material, such as tungsten silicide, thereon. The decoupling capacitors' dielectric can be formed from high dielectric constant materials, such as TEOS, oxide, nitride or any combination thereof. The second decoupling capacitor could be fabricated over field oxide and used as a single capacitor having a first and second conductively doped polysilicon electrodes (either silicided or non-silicided) with a capacitor dielectric sandwiched in between.

On chip decoupling capacitor

Disclosed is a baffle apparatus for insertion into a semiconductor wafer processing furnace to diffuse processing gases that are injected into the furnace by an injector nozzle. The baffle apparatus comprises:

Semiconductor processing gas diffuser plate

In the present invention, a stable and uniform texturized surface of a conductive structure is developed by annealing, oxidizing and etching a layer of metal silicide that has been deposited over a semiconductive material. Using this process during fabrication of memory cell in a DRAM will increase storage node capacitance by creating texturized capacitor cell plates that will retain their textured surfaces throughout implementation of conventional DRAM fabrication processes.

Metal silicide texturizing technique

A mini-stack capacitor process, developed for DRAM fabrication, is used to create a stacked capacitor by depositing multiple layers of dielectric over existing digit and word lines. The exposed top dielectric is then masked and etched away between two adjacent digit lines, the resist is stripped and subsequent etches (or etch) remove(s) the remaining dielectric layers thereby exposing the underlying conductively doped diffusion region. The storage node poly is then deposited and patterned, followed by subsequent depositions of a cell dielectric and cell plate poly. The selection of the number of dielectrics used and the type and/or sequence of dielectric etches used are the crux of the invention that substantially increases the surface area of a given stacked capacitor by approximately 40 to 80%.

Method of increasing the surface area of a mini-stacked capacitor

Disclosed is a baffle apparatus for insertion into a semiconductor wafer processing furnace to diffuse processing gases that are injected into the furnace by an injector nozzle. The baffle apparatus comprises: a diffuser plate assembly having an upper end and a lower end, the diffuser plate assembly having at least one diffuser plate against which injected gases are to be forced; and the lower end of the diffuser plate assembly being sized and shaped to engage with and be supported by an elongated wafer paddle.

An apparatus used to HF gas etch a plurality of integrated circuit wafers within an etch chamber, followed by a de-ionized water cascade rinse in the chamber. On completion of the rinse and removal of the wafer carriers, the apparatus, housing, and supply conduits are purged with an inert gas to prepare the apparatus for a next batch of wafer carriers. The apparatus includes process-control means for automatically controlling each step of the process.

Hydrofluoric acid etcher and cascade rinser

A process for forming silicon dioxide, SiO.sub.2, or silicon nitride, Si.sub.3 N.sub.4, layers on selected substrates which includes reacting diethylsilane, C.sub.4 H.sub.12 Si, with a selected oxygen-containing compound or nitrogen-containing compound in a plasma enhanced chemical vapor deposition (PECVD) chamber. The conformality of the coatings thus formed is in the range of 85% to 98%. The diethylsilane liquid source for the associated gas flow processing system may be maintained and operated at a source temperature as low as room temperature.

Process for forming highly conformal dielectric coatings in the

Disclosed is a semiconductor processing furnace flow restricting apparatus for insertion into a longitudinally elongated semiconductor wafer processing furnace to create back pressure to increase residence time of processing gases within the furnace. The apparatus comprises:

Semiconductor processing apparatus for creating back pressure within a

Disclosed is a quartz tube for a furnace for processing semiconductor wafers. The furnace comprises:

Semiconductor processing furnace tube and alignment jig

An R-F electrode apparatus is provided featuring self-adjusting, spring biased electrodes, removably attached to a removable substrate holder, within a chamber used for plasma reactive treatment processes, particularly those involving semiconductor wafers. The apparatus further features base electrodes shaped and supported to insure uniform transmission of electrical energy during operation. The apparatus also provides an automatic means for wiping, self-cleaning action between the contact surfaces of opposing electrodes during introduction and removal of the substrate holder from the reaction chamber. The base electrodes are removably attached to standard electrical feedthroughs located in the reaction chamber wall, which lead to an external R-F power supply.

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Boise, ID, United States of America

Navjot Chhabra