Texas Instruments Corporation

Navinchandra Kalidas

Michael A Lamson

Raymond W Thompson

John H Abbott

Jeremias Perez Libres

Nozar Hassanzadeh

Michael P Pierce

Masood Murtuza

William P Stearns

David S Laffitte

A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias. Said signal lines being distributed relative to said first power lines such that the inductive coupling between them reaches at least a minimum value, providing high mutual inductances and minimized effective self-inductance. Said signal lines further being electromagnetically coupled to said ground metal such that cross talk between signal lines is minimized. And an outermost insulating film protecting the exposed surfaces of said signal and power lines, said film having a plurality of openings filled with metal suitable for contacting selected signal and power lines and chip solder bumps.

Structure and method of high performance two layer ball grid array substrate

Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate with first and second surfaces, at least one opening, and a certain thickness. On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads; at least one of the contact pads is electrically connected with at least one of the routing strips, and may have a solder body attached. A semiconductor chip is positioned in the opening while leaving a gap to the substrate; the chip has an active surface including at least one bond pad, and a passive surface substantially coplanar with the second substrate surface. Substrate thickness and chip thickness may be substantially equal. Bonding elements bridge the gap to connect electrically bond pad and routing strip. Encapsulation material protects the active chip surface and the bonding elements, and fills the gap so that the filler surface is substantially coplanar with the passive chip surface and the second substrate surface. The support tape used in assembly is discarded.

Low profile, chip-scale package and method of fabrication

Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate () with first and second surfaces (), at least one opening (), and a certain thickness (). On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads (); at least one of the contact pads is electrically connected with at least one of the routing strips, and may have a solder body () attached. A semiconductor chip () is positioned in the opening while leaving a gap () to the substrate; the chip has an active surface () including at least one bond pad (), and a passive surface () substantially coplanar with the second substrate surface (). Substrate thickness and chip thickness may be substantially equal. Bonding elements () bridge the gap to connect electrically bond pad and routing strip. Encapsulation material () protects the active chip surface and the bonding elements, and fills the gap so that the filler surface () is substantially coplanar with the passive chip surface and the second substrate surface. The support tape () used in assembly is discarded.

A package for a flip chip integrated circuit including an interposer with electrical interconnecting for signal, power, and ground contacts. Routing is accomplished on only two conductor layers through the use of selective planes and buses. Multiple power planes are provided on a single conductor level to support circuits having different operating voltages. A unique cavity down BGA package for a flip chip interconnected integrated circuit is provided by adhering the interposer to a thermally conductive stiffener or base, and using solder balls to attach the frame to the base and interposer. The assemblage forms a chip cavity with interconnecting vias to external BGA solder balls terminals located in the perimeter frame.

Ball grid package with multiple power/ground planes

A ball grid array package (10) is provided that includes a heat spreader (14), a stiffener (13), a substrate (16), and a die or chip (12). The stiffener (13) is mounted to the heat spreader (14) and has a cavity formed therein. The stiffener (13) may serve as either a ground plane or a power plane of ball grid array package (10), depending on the desired implementation. The substrate (16) includes a signal plane (30) and a power bus (28) on a first surface and has a cavity formed therein. The substrate (16) is mounted to the stiffener (13) through a second surface. The substrate (16) further having at least one hole formed from the first surface to the second surface and a plurality of solder balls, similar to solder ball (20), to provide an external connection to the ball grid array package (10). Finally, the chip (12) is mounted to portion of the heat spreader (14) exposed through the cavity of the substrate (16) and the stiffener (13) and wire bonded to the various electrical planes, including the stiffener (13). The present invention also provides a method (100) for forming the ball grid array package (10) of the present invention.

Ball grid array package

In accordance with the invention, integrated circuit dies may be packaged in a plastic package employing an area area array technology such as a conductive ball grid array, column grid array or pin grid array. One aspect of the invention is an integrated circuit package (10) which includes an electronic circuit enclosed by a plastic body (12, 14). The molded plastic body has a first major surface opposing a second major surface. The first major surface of integrated circuit (10) has a plurality of openings therein. One of a plurality of conductive pads (18) is adjacent to each one of the openings and is electrically connected to the electronic circuit. Each of a plurality of conductors (20) is electrically connected to one of the pads (18) and protrudes from one of the openings (22).

Method of making plastic package for a surface mounted integrated circuit

A ball grid array package (62) having a deformable metal layer (20) is provided that includes a heat spreader (60), a stiffener (40) having a cavity and mounted to the heat spreader (60), a substrate (22), and a die (50). The substrate (22) includes a dielectric layer (10) with a cavity and cut-outs, the deformable metal layer (20), and a plurality of electrical traces for connection to solder balls. The dielectric layer (10) couples to the stiffener (40) through a second side and to the deformable metal layer (20) through the first side. The deformable metal layer (20) includes a cavity, a power ring (26), a ground ring (24), and a plurality of traces serving as either a ground connection, a signal connection, or a power connection for coupling with the plurality of solder balls. The deformable metal layer (20) also has a plurality of deformable metal layer portions each partially positioned over one of the cut-outs in the dielectric layer (10) and electrically coupled to the stiffener (40) through the cut-out. Each of the plurality of deformable metal layer portions also couples with one or more of the plurality of traces. The die (50) is mounted to the heat spreader (60) through the cavity of the substrate (22) and the stiffener (40). The present invention also provides a method for forming the ball grid array package (62).

Ball grid array package having a deformable metal layer and method

In accordance with the invention, integrated circuit dies may be packaged in a plastic package employing an area area array technology such as a conductive ball grid array, column grid array or pin grid array. One aspect of the invention is an integrated circuit package(10) which includes an electronic circuit enclosed by a plastic body (12, 14). The molded plastic body has a first major surface opposing a second major surface. The first major surface of integrated circuit (10) has a plurality of openings therein. One of a plurality of conductive pads (18) is adjacent to each one of the openings and is electrically connected to the electronic circuit. Each of a plurality of conductors (20) is electrically connected to one of the pads (18) and protrudes from one of the openings (22).

Plastic packaging for a surface mounted integrated circuit

An electronic connection socket for connecting an electronic package and including a body of nonconductive material, an electronic device fabricated upon a semiconductor substrate located upon the body. The electronic device includes several bonding pads. The socket includes a set of pins to provide interconnection to external electronic devices. The body also includes pin sockets providing interconnection to the electronic package. The pins and pin sockets of the body are also connected to the bonding pads of the electronic device. To provide the electrical interconnection between the electronic package, the electronic device located upon the semiconductor substrate in the socket body and the external circuitry connected to the body.

Growing community of inventors

Houston, TX, United States of America

Navinchandra Kalidas