Globalfoundries Inc.

International Business Machines Corporation

Arm Limited

Navin Agarwal

Krishnan Santhana Rengarajan

Igor Arsovski

Venkatraghavan Bringivijayaraghavan

Toshiaki Kirihata

Fakhruddin Ali Bohra

Lalit Gupta

Shri Sagar Dwivedi

Jitendra Dasani

Rajiv Kumar Sisodia

Ramesh Raghavan

Balaji Jayaraman

Janakiraman Viraraghavan

Rajesh Reddy Tummuru

Jay M Shah

Thejas Kempanna

Daksheshkumar Maganbhai Malaviya

Aditya S Auyisetty

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.

Providing a discharge boundary using bitline discharge control circuitry for an integrated circuit

A circuit structure is provided. The circuit structure includes first pfet device. The circuit structure further includes a first nfet device connected to the pfet device. The circuit structure further includes a keeper nfet device that reduces stress associated with the first nfet device by keeping the first nfet device off during its functional state. The circuit structure further includes a keeper pfet device that reduces stress associated with the first pfet device by keeping the first pfet device off during its functional state.

Minimization of bias temperature instability (BTI) degradation in circuits

Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device of the cell array which comprises a third device which is connected to a source line and the node and controlled by the word line and a fourth device which is connected between the word line and the node. In the memory, in response to another word line in the cell array being activated and the word line not being activated to keep the first device in an unprogrammed state, the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to a voltage level around zero volts.

Disturb free bitcell and array

A memory device with an age-detect-and-correct (ADAC) circuit that detects skew caused by bias temperature instability fatigue (that is, bias temperature instability stress accumulated over time), and counters skew by selectively adjusting the proportion (measured temporally) of active state operation to idle state operation. Also, a memory burn-in device using a similar ADAC circuit.

Bias temperature instability state detection and correction

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Bengaluru, India

Navin Agarwal