Intel Corporation

Cadence Design Systems, Inc.

Rambus Inc.

Navid Yaghini

Robert H Wang

Sida Shen

Zhuobin Li

Antonios Pialis

Rafal Karakiewicz

Rajeevan Mahadevan

Raymond Kwok Kei Tang

Hemesh Yasotharan

Clifford Ting

Mark Andruchow

Nicola Pantaleo

Mohammadamin Karami

Mike Bichan

Robert Wang

Multiple voltage amplitudes for an oscillator in a phase-locked loop may be selected to meet various design goals/criteria (e.g., frequency range of operation, jitter, power consumption, etc.). These multiple voltage amplitudes may be stored in a lookup table memory that relates frequency ranges to reference voltages. A reference voltage for a particular oscillator may then be selected and generated. A feedback loop may compare the amplitude output by the oscillator to the reference voltage and adjusts a bias current of the oscillator with the goal of substantially equalizing the oscillator output to the reference voltage.

Oscillator amplitude calibration

A circuit and method are described for generating a low jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing the high-frequency clock by the reference clock and phase locking the output clock to the high-frequency clock. Non-integer divide ratios can be achieved by dividing the high-frequency clock by the nearest integer, rounded down, and then delaying the resultant output clock by the modulus of the division. The delay can then be rotated across to create a clock with a non-integer divide ratio relative to the high-frequency clock. By doing so, a high-frequency clock may be used that is not constrained by having a frequency that is an integer multiple of each desired component-specific output clock signal.

Low jitter clock multiplier circuit and method with arbitrary frequency acquisition

A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.

Circuit and method to set delay between two periodic signals with unknown phase relationship

A system and method providing power supply rejection. One embodiment provides for power supply rejection in PLL or DLL circuitry. First subcircuitry provides second subcircuitry a supply voltage which is a filtered version of power from an external source. The first subcircuitry includes a first field effect transistor and a first low pass filter coupled to receive a signal from the external power source during operation of the second subcircuitry. The filter is coupled to provide a filtered version of the power source signal to the gate of the first transistor, so that when a first source/drain region of the first transistor is connected to receive power from the external source and the gate of the first transistor receives the filtered version of the power source signal, the second source/drain region of the first transistor provides a first modified version of the power received from the external source.

System incorporating power supply rejection circuitry and related method

Systems, methods and circuitry useful for adjusting a periodic signal such as with a voltage controlled oscillator or a delay line. In one series of embodiments, circuits and methods are provided for controlling current flow through first and second parallel paths where an impedance device in one path emulates the impedance characteristics of a different device in the other path. A phase or frequency characteristic of the periodic signal may be adjusted by alternate switching of current through the two paths.

System, method and emulation circuitry useful for adjusting a characteristic of a periodic signal

A system incorporating and method of operating phase locked loop circuitry. In one embodiment, having programmable circuitry for adjustment of loop dynamics, a VCO has a first input terminal for selecting phase and frequency characteristics of an output signal and an output terminal on which the output signal is provided. A detector generates first VCO input signals indicative of phase and frequency differences between the VCO output signal and a reference signal. Circuitry digitizes the first VCO input signals and generates an integral path input signal therefrom. Slow integral path circuitry comprising, a first transistor device and a programmable low pass filter: receives the integral path input signal, and provides a low pass filtered version of the integral path input signal to control conduction through the first transistor device and provide a first adjustment signal for adjustment of the frequency of the VCO output signal.

System and method providing bandwidth adjustment in integral path of phase locked loop circuitry

System and method providing multiple circuit paths to control characteristics of periodic signals. In one embodiment first and second detector signals are indicative of a phase and frequency differences between the output signal and a reference signal. A first input signal based on the first detector signal adjusts the phase difference. A first control signal based on the second detector signal has frequency content in high and low frequency ranges. A second input signal based on the control signal reduces the frequency difference. A second control signal based on the second detector signal has relatively low frequency content in the high frequency range. A third input signal based on the second control signal reduces the frequency difference.

System including circuitry providing multiple circuit paths for controlling a characteristic of a period signal

Circuits and methods for controlling a VCO output signal. A filtered version of an integral path input signal controls current flow through a proportional path. An exemplary embodiment generates an integral path input signal from a digital to analog converter. First integral path circuitry includes a first transistor device and a low pass filter which provides a filtered version of the integral path input signal to a first transistor device to control conduction through the device, providing a first VCO input signal for frequency adjustment of the output signal. Proportional path switching circuitry between a supply terminal and VCO input terminal includes a second transistor device which receives the first VCO input signals to control conduction between the supply terminal and the first VCO input terminal to provide a second signal for adjustment of the phase of the VCO output signal relative to the reference signal.

System and method for adjusting a characteristic of a periodic signal with use of a filtered bias voltage

System and circuitry controlling characteristics of periodic signals. In one embodiment adjustment circuitry modifies periodic signal characteristic. A phase detector generates analog input signals indicative of a phase difference between the periodic signal and a reference signal. Conversion circuitry translates the analog input signals into digital signals. Signal driving circuitry, comprising a current source, provides control signals to the signal driving circuitry based on the digital signals. First input circuitry provides a first adjustment signal to the adjustment circuitry. Second input circuitry provides a second adjustment signal to the adjustment circuitry in response to the control signal. The first adjustment signal is based on input of analog signals to a circuit element in the first input circuitry to control the first adjustment signal. The second input circuitry is responsive to the control signal to provide the second adjustment signal with the digital version of the input signals.

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Pickering, Canada

Navid Yaghini