Qualcomm Incorporated

Intel Corporation

Navid Toosizadeh

Shih-Hsin Jason Hu

Mohammad Reza Kakoee

Keith Alan Bowman

Mohamed Waleed Allam

Altug Koker

Kamal Sinha

Nan Chen

Nam Dang

Yu Huang

Lam Ho

Sorin Adrian Dobre

Saravana Krishnan Kannan

Min Chen

Pawan Chhabra

Sarbartha Banerjee

Jasmin Smaila Ibrahimovic

Carlos Auyon

Sreekanth Nallagatla

An all-digital closed-loop fine-grained control of voltage and frequency for running conditions of a compute machine such as graphic processor unit (GPU), central processing unit (CPU), or any other processing unit. The scheme optimizes the voltage margin and frequency on the fly according to desired programmable performance metrics. A mitigation response to droops is naturally built into the system and is equal to the cause rather than being excessive. The scheme is scalable and can be instantiated in different clusters for best results.

Workload based adaptive voltage and frequency control apparatus and method

A programmable delay line includes a pulse generator configured to generate a pulse in response to a transition of an input signal; an oscillator configured to generate a clock in response to the pulse; a counter configured to change a current count from a first value towards a second value in response to periods of the clock; and a gating device configured to output the transition of the input signal to generate an output signal in response to the current count reaching the second value. The delay of the input signal is a function of the difference between the first value and the second value. The delay line may be used in different applications, such as a dynamic variation monitor (DVM) configured to detect supply voltage droop. The DVM may be in an adaptive clock distribution (ACD) to reduce the clock frequency for a datapath in response to a droop.

Ring oscillator-based programmable delay line

A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.

Active-core-based performance boost

In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.

Dynamically adaptive voltage-frequency guardband control circuit

A method including receiving an indication of a number of active processing units in a computer processor; in response to receiving the indication, determining an appropriate operating voltage margin for the computer processor; reducing an operating frequency of the active processing units in response to receiving the indication; adjusting a power supply to increase or decrease a voltage to the computer processor in accordance with the appropriate operating voltage margin; and increasing the operating frequency of the active processing units in response to an acknowledgment that the power supply has been adjusted.

Circuits and methods providing voltage adjustment as processor cores become active based on an observed number of ring oscillator clock ticks

An integrated circuit compensates for circuit aging by measuring the aging with an aging sensor and controlling a supply voltage based on the measured aging. The operating environment for the aging sensor can be set to reduce impacts of non-aging effects on the measured aging. For example, the operating environment can use a temperature inversion voltage. An initial aging measurement value which is the difference between an initial aged measurement and an initial unaged measurement can be stored on the integrated circuit. A core power reduction controller can use the measured aging and the stored initial aging measurement value to update a performance-sensor target value and then perform adaptive voltage scaling using the using the updated performance-sensor target value.

Integrated circuit adaptive voltage scaling with de-aging

Growing community of inventors

San Diego, CA, United States of America

Navid Toosizadeh