University of Florida Research Foundation Inc

University of Connecticut

Navid Asadizanjani

Domenic J Forte

Mark M Tehranipoor

Damon Woodard

Haoting Shen

Ronald Wilson

Swarup Bhunia

Nidish Vashistha

Bicky Shakya

Mir Tanjidur Rahman

Qihang Shi

Systems and methods are configured to generate a frequency map representing a density of objects found in regions of a sample that may be used in setting parameters for imaging the regions. Various embodiments involve binarizing the pixels for a raw image of the sample to transform the image into binary data. Run-length encoded components are identified from the data for dimensions of the raw image. Each component is a length of a sequence of adjacent pixels found in a dimension with the same value in the binary data. A projection of the image is then generated from projection values for the dimensions. Each projection value provides a measure of the density of objects present in a dimension with respect to the components identified for the dimension. This projection is used to identify a level of density for each region of the sample from which the frequency map is generated.

Automatic sharpness adjustment for imaging modalities

A pyramid structure to mitigate optical probing attacks in ICs by scrambling the measurements reflected by a laser pulse is disclosed. The pyramid structure is applied to selected areas at the bottom surface of the metal traces in metal layer to circumvent the extra silicon layer and thus minimize the changes to the conventional device structures. The pyramid structure includes randomized pyramids at nanometer scale. Optical simulation results show the pyramidized metal surface is able to prevent optical probing attacks. The fabrication of pyramids is CMOS compatible as well. Optical simulations are performed to analyze the impact these nano-scaled pyramids in a laser voltage probing attacking model. The nanopyramid can disturb the optical measurements enough to make the attacks practically infeasible. In addition, the nanopyramid structure countermeasure works in a passive mode without consuming any energy.

Optical scrambler with nano-pyramids

A histogram-based method for auto segmentation of integrated circuit structures is disclosed. The method includes an auto-segmentation process/algorithm, which works on the histogram of the SEM image and does not try to model the noise sources or the features. The auto-segmentation process/algorithm extracts the number of peaks in the histogram from low magnification SEM images or SEM images not necessarily having high quality images, significantly simplifies the traditionally lengthy and expensive IC reverse engineering efforts. Hence, the size of the image does not affect the final segmentation. The auto-segmentation process/algorithm performs the steps of: extract a first histogram from the first SEM image; identifying boundaries of the plurality of structural elements in the IC based at least in part on an output of the first histogram; and auto-segmenting the first SEM image into the plurality of structural elements.

Histogram-based method for auto segmentation of integrated circuit structures from SEM images

Methods and apparatus are provided for automatically extracting standard cells to form a standard cell library using raw multi-layer images of an IC. Accordingly, various embodiments involve: extracting the raw contact layer image from the raw multi-layer images; binarizing the raw contact layer image to generate a binarized contact layer image identifying a plurality of contact rows and a plurality of contact columns; determining a plurality of Vlines based on a subset of the plurality of contact rows having a periodic nature; extracting a plurality of binarized contact layer image strips from the binarized contact layer image; encoding each binarized contact layer image strip using feature vectors and column distance values; applying a model rule set to each encoded binarized contact layer image strip for detecting cell boundaries; extracting the standard cells based on the cell boundaries; and storing the extracted cells to form a standard cell candidate library.

Method and apparatus for automatic extraction of standard cells to generate a standard cell candidate library

Circuits and methods for protecting against intellectual property piracy and integrated circuit piracy from an untrusted third party are provided. A circuit can include an original circuit and an obfuscated circuit incorporated into the original circuit and changing the output of the original circuit, wherein the obfuscated circuit is configured to recover the output of the original circuit by modifying the obfuscated circuit. In addition, a method of manufacturing a semiconductor device can include designing a circuit including an original circuit and an obfuscated circuit, and fabricating the circuit, wherein the obfuscated circuit is configured to change an output of the original circuit and to recover the output of the original circuit by modifying the obfuscated circuit.

Circuit edit and obfuscation for trusted chip fabrication

A method of detecting hardware Trojans in an IC includes providing a golden IC layout data set or SEM image data taken at long dwelling time on an active area of the golden IC after polishing it from the backside. Next, the IC under authentication (IUA) sample is prepared for fast SEM imagining (shorter dwelling time) after backside thinning. Next step is to perform image processing on the IUA's SEM image, which includes histogram equalization with noise filtering using Gaussian and Median filters. In the last step, the IUA sample data with the shorter dwelling time is compared with the golden IC layout data or the golden image data from high quality (longer dwelling time) SEM scanning process. At the end the result of the comparison is used to identify hardware Trojans.

Hardware trojan scanner

A method of assessing vulnerability of Integrated Circuit (IC) can include: preparing a list of logic nets of the IC; obtaining rectangular segments from the logic nets; finding a milling exclusion area based on a covering wire; and superimposing the found milling exclusion area onto the rectangular segments of the logic nets. The milling exclusion area is an area that microprobing attack does not succeed without cutting off at least one of the rectangular segments.

Layout-driven method to assess vulnerability of ICs to microprobing attacks

A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an insulator interposed between the first metal trace and the first via. The insulator can be configured to lower an energy barrier or redistribute structure defects or charge carriers, such that the first metal trace and the first via are electrically connected to each other when power is applied. The semiconductor device can further include a dummy via disposed on the first metal trace.

Growing community of inventors

Gainesville, FL, United States of America

Navid Asadizanjani