Synopsys, Inc.

Navendu Sinha

Akash Renukadas Deshpande

Roberto Attias

Vineet Gupta

Shobhit Sonakiya

William Charles Jordan

Stephen John Joseph Fricke

Bryon Irwin Moyer

Anirban Banerjee

AI-assisted Connected Home systems for improving power efficiency at homes and offices are described. The system may perform operations including: receiving, from each of a plurality of power receptacles, power usage information of an electrical device attached to the power receptacle; determining, for each of the plurality of power receptacles, a plurality of power usage metrics of the power receptacle based on the power usage information; feeding the plurality of power usage metrics into a machine learning model to obtain a priority of the electrical device attached to the power receptacle, wherein the priority is one of a plurality of pre-configured priorities; obtaining a power management signal; and transmitting a plurality of control signals to the plurality of power receptacles based on the power management signal and respective priorities of the plurality of electrical devices attached to the plurality of power receptacles.

Method and system for AI-powered smart homes and offices

System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

Hardware accelerator test harness generation

Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.

Structured block transfer module, system architecture, and method for transferring

Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host., the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.

Generating hardware accelerators and processor offloads

Packet ingress/egress block and logic and system and method for receiving, transmitting, and managing packetized data. System including a line port; a computing resource output port; a host interface; a memory, and a block that: receives information on the line port, creates a context including information for managing computation derived from the received information, and sends context out on computing resource output port. Device comprising first circuit component including line port that receives information, second circuit component that generates context information including an information for managing computation derived from the received unit of information; and third circuit component that communicates the generated context out to a computing resource output port. Method comprising receiving information, generating context information including an information for managing computation derived from the received unit of information; and communicating the generated context information out to an external receiver via a computing resource output port.

Growing community of inventors

Milpitas, CA, United States of America

Navendu Sinha