Princeton University

Analog Devices,inc.

Naveen Verma

James Christopher Sturm

Sigurd Richard Wagner

Hossein Valavi

Hongyang Jia

Zhuo Wang

Jintao Zhang

Yingzhe Hu

Liechao Huang

Eric G Nestler

Kyong Ho Lee

Branko Glisic

Jinseok Lee

Yue Ma

Can Wu

Systems and methods disclosed herein provide for a passive backscattering beamformer based on large-area electronics (LAE). Low power is critical for distributed nodes in future IoT/5G networks. A key emerging solution is using ubiquitous 2.4 GHz Wi-Fi infrastructure with passive backscattering nodes, for low-power communication. LAE enables monolithic integration of devices over large and flexible substrates, with recent advances into the gigahertz regime opening new opportunities for wireless systems. An LAE passive backscattering beamformer is chosen that is capable of (1) enhancing the backscattered signal power in a scalable manner enabled by LAE's monolithic integrability over meter-scale area; (2) configuration between constructive/destructive beamforming; (3) frequency-shift keying for data modulation and SNR enhancement, by shifting the signal away from the incident interferer; and (4) frequency division multiplexing for increasing data bandwidth.

Passive backscattering beamformer based on large-area electronics

Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

Analog switched-capacitor neural network

Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

Configurable in memory computing engine, platform, bit cells and layouts therefore

Various embodiments comprise systems, methods, architectures, mechanisms, apparatus, and improvements thereof for in-memory computing using charge-domain circuit operation to provide energy efficient, high speed, capacitor-based in-memory computing. Various embodiments contemplate controlling input signal presentation within in-memory computing structures/macros in accordance with predefined or dynamic switch selection criteria to reduce energy consumption associated with charging and/or discharging summing capacitors during reset and evaluation operating modes of multiplying bit-cells (M-BCs).

Efficient reset and evaluation operation of multiplying bit-cells for in-memory computing

A heterogeneous microprocessor configured to perform classification on an input signal. The heterogeneous microprocessor includes a die with a central processing unit (CPU) a programmable feature-extraction accelerator (FEA) and a classifier. The FEA is configured to perform feature extraction on the input signal to generate feature data. The classifier is configured to perform classification on the feature data and the CPU is configured to provide processing after classification. The FEA may be configured with a plurality of Gene-Computation (GC) Cores. The FEA may be configured for genetic programing with gene depth constraints, gene number constraints and base function constraints. The classifier may be a support-vector machine accelerator (SVMA). The SVMA may include training data based on error-affected feature data. The heterogeneous microprocessor may also include an automatic-programming & classifier training module. An automatic-programming & classifier training module may be configured to receive input-output feature data and training labels and generate gene code and a classifier model.

Heterogeneous microprocessor for energy-scalable sensor inference using genetic programming

A weak binary classifier configured to receive an input signal for classification and generate a classification output is disclosed. The weak binary classifier includes a plurality of weighting amplifier stages, each weighting amplifier stage being configured to receive the input signal for classification and a weighting input derived from a classifier model and generate a weighted input signal, the plurality of weighting amplifier stages being configured to generate a plurality of positive weighted input signals coupled to a positive summing node and a plurality of negative weighted input signals coupled to a negative summing node. The weak binary classifier also includes a comparator having a non-inverting input coupled to the positive summing node and an inverting input coupled to the negative summing node and being configured to generate a weak classification output based on the plurality of weighted input signals.

Machine-learning classifier based on comparators for direct inference on analog sensor data

A three dimensional touch sensing system having a touch surface configured to detect a touch input located above the touch surface is disclosed. The system includes a plurality of capacitive touch sensing electrodes disposed on the touch surface, each electrode having a baseline capacitance and a touch capacitance based on the touch input. An oscillating plane is disposed below the touch surface. A touch detector is configured to drive one of the touch sensing electrodes with an AC signal having a frequency that shifts from a baseline frequency to a touch frequency based on the change in electrode capacitance from the baseline capacitance to the touch capacitance. The touch detector is configured to drive the oscillating plane to the touch frequency.

System and method for 3D position and gesture sensing of human hand

A multiplying analog to digital converter including an analog to digital converter (ADC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter. A feedback attenuator is disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output. A barrel shifter is configured to provide digital multiplication of the ADC output. The feedback attenuator may be configured as a divider network. The feedback attenuator may be configured to provide attenuation using only passive components. The feedback attenuator may be configured as a capacitive divider network. The feedback attenuator may be configured to provide attenuation ranging between 1 and 0.5.

Multiplying analog to digital converter and method

A machine-learning accelerator (MLA) integrated circuit for extracting features from signals and performing inference computations is disclosed. The MLA integrated circuit includes a framework of finite state machine (FSM) kernels that are machine-learning algorithms implemented in hardware. The MLA integrated circuit further includes a kernel controller having mathematical structures implemented in hardware in communication with the framework of FSM kernels. An arithmetic engine implemented in hardware within the MLA integrated circuit is in communication with the kernel controller to perform computations for the mathematical structures. In at least one embodiment, the MLA integrated circuit includes a compression decompression accelerator (CDA) implemented in hardware and coupled between a memory and the kernel controller for compressing data to be stored in the memory and for decompressing data retrieved from the memory.

Machine-learning accelerator (MLA) integrated circuit for extracting features from signals and performing inference computations

A multiplying analog to digital converter (ADC) including a successive-approximation-register (SAR) analog to digital converter (ADC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter. A feedback attenuator is disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output. A barrel shifter is configured to provide digital multiplication of the ADC output. The feedback attenuator may be configured as a divider network. The feedback attenuator may be configured to provide attenuation using only passive components. The feedback attenuator may be configured as a capacitive divider network. The feedback attenuator may be configured to provide attenuation ranging between 1 and 0.5.

A system and method for interfacing large-area electronics with integrated circuit devices is provided. The system may be implemented in an electronic device including a large area electronic (LAE) device disposed on a substrate. An integrated circuit IC is disposed on the substrate. A non-contact interface is disposed on the substrate and coupled between the LAE device and the IC. The non-contact interface is configured to provide at least one of a data acquisition path or control path between the LAE device and the IC.

Growing community of inventors

Princeton, NJ, United States of America

Naveen Verma