Texas Instruments Corporation

Other

Naveen Mahadev

Shagun Dusad

Yogesh Darwhekar

Himamshu Gopalakrishna Khasnis

Srikanth Manian

Pranav Kumar

Arpan Sureshbhai Thakkar

Vysakh Karthikeyan

Anantha Melavarige Subraya

Rafi Mahammad

A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.

Balun with improved common mode rejection ratio

A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.

Phase error reduction in a receiver

Methods and circuits for maximizing gain of a voltage follower circuit are provided. The method includes using a NMOS voltage replica generation circuit, a PMOS voltage replica generation circuit, a NPN BJT voltage replica generation circuit, a n-channel JFET voltage replica generation circuit, a P-Channel JFET voltage replica generation circuit and a PNP BJT voltage replica generation circuit. The overall gain for the various transistor families is almost equal to unity.

Voltage follower circuit to mitigate gain loss caused by finite output impedance of transistors

A method and system of synthesizing impedance in a radio frequency (RF) amplifier includes receiving a voltage signal at a passive mixer. The passive mixer down-converts the voltage signal into a baseband frequency. The method includes converting the voltage signal into a digital signal. Further, the method includes performing convolution of the digital signal with an impulse response. The impulse response is of a low Q impedance and is programmable. Furthermore the method includes generating a current signal based on output of the convolution. Furthermore the method includes performing up-conversion of the current signal in the passive mixer. The passive mixer performs impedance transformation of the low Q impedance. Moreover, the method includes providing the current signal via the passive mixer to synthesize desired impedance in the RF amplifier, thereby controlling frequency response of the RF amplifier.

Impedance synthesis for optimum frequency response of a radio frequency (RF) amplifier

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Bengaluru, India

Naveen Mahadev