Nvidia Corporation

Naveen Leekha

Jeffrey A Bolz

Ignacio Llamas

Philip Alexander Cuadra

Jesse David Hall

Daniel Elliot Wexler

One embodiment of the present invention sets forth a technique for performing low latency computation on a parallel processing subsystem. A low latency functional node is exposed to an operating system. The low latency functional node and a generic functional node are configured to target the same underlying processor resource within the parallel processing subsystem. The operating system stores low latency tasks generated by a user application within a low latency command buffer associated with the low latency functional node. The parallel processing subsystem advantageously executes tasks from the low latency command buffer prior to completing execution of tasks in the generic command buffer, thereby reducing completion latency for the low latency tasks.

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Durham, NC, United States of America

Naveen Leekha