Intel Corporation

Naveen Kumar M

Gururaj Shamanna

Iqbal Rajwani

Pascal Meinerzhagen

Harishankar Sahu

Jagadeesh Chandra Salaka

Madhusudan Rao

Sravan K Puchakayala

Abhishek Chouksey

Circuits for optimizing the duration of a sense amp enable signal in a memory device such as SRAM.

Apparatus and method to optimize sense-amp enable pulse-width in SRAM arrays

An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.

Keeper-free integrated clock gate circuit

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Bengaluru, India

Naveen Kumar M