Micron Technology Incorporated

Naveen Kaushik

Haitao Liu

Sidhartha Gupta

Richard J Hill

Pankaj Sharma

Kyle A Ritter

Tomoko Ogura Iwasaki

Yoshihiko Kamata

Deepak Chandra Pandey

Yoshiaki Fukuzumi

Violante Moschiano

Fatma Arzum Simsek-Ege

Aaron S Yip

Paolo Tessariol

June Lee

Jian Li

Xiaojiang Guo

Collin Howder

Adam L Olson

Albert Fayrushin

Lars P Heineck

David Ross Economy

Harsh Narendrakumar Jain

Litao Yang

Shuai Xu

Venkata Naveen Kumar Neelapala

Chittoor Ranganathan Parthasarathy

Sonam Jain

Gaurav Musalgaonkar

Some embodiments include an integrated assembly having a channel-material-pillar extending vertically through a stack of alternating conductive levels and insulative levels. The channel-material-pillar includes a first semiconductor material. A second semiconductor material is directly against an upper region of the channel-material-pillar. The second semiconductor material has a higher dopant concentration than the first semiconductor material and joins to the first semiconductor along an abrupt interfacial region such that there is little to no mixing of dopant from the second semiconductor material into the first semiconductor material. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material with vertical extensions that protrude to an interface with the channel material at an elevation proximate at least one source-side GIDL region. Slit structures extend through the stack structure to divide the structure into blocks of pillar arrays. A series of spaced, discrete pedestal structures are included along a base of the slit structures. Forming the microelectronic device structure may include forming a lateral opening through cell materials of the pillar, vertically recessing the channel material, and laterally recessing other material(s) of the pillar before forming the doped material in the broadened recesses. Additional microelectronic devices, related methods, and electronic systems are also disclosed.

Microelectronic devices with vertically recessed channel structures and discrete, spaced inter-slit structures, and related methods and systems

An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

Electronic devices comprising multilevel bitlines, and related methods and systems

A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

Apparatuses including device structures including pillar structures

A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material is formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.

Memory array and method used in forming a memory array

An apparatus includes lightly doped drain regions vertically extending into a semiconductor substrate. A channel region is horizontally interposed between the lightly doped drain regions, and source/drain regions vertically extend into the lightly doped drain regions. Breakdown-enhancement implant intrusion regions are within the lightly doped drain regions and are horizontally interposed between the channel region and the source/drain regions. The breakdown enhancement implant regions have a different chemical species than the lightly doped drain regions and have upper boundaries vertically underlying upper boundaries of the lightly doped drain regions. The apparatus also has a gate structure vertically overlying the channel regions and it is horizontally interposed between the breakdown-enhancement implant regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Altering breakdown voltages in gate devices and related methods and systems

Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.

Capacitor in a three-dimensional memory structure

Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source.

Integrated assemblies having conductive-shield-structures between linear-conductive-structures

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first pillar of a first memory cell string; a second pillar of a second memory cell string; a first conductive structure extending in a first direction, the first conductive structure located over and in electrical contact with the first pillar; a second conductive structure extending in the first direction, the second conductive structure located over and in electrical contact with the second pillar; a select gate coupled to the first and second memory cell strings; a first data line located on a first level of the apparatus and extending in a second direction, the first data line located over the first conductive structure and in electrical contact with the first conductive structure; and a second data line located on a second level of the apparatus and extending in the second direction, the second data line located over the second conductive structure and in electrical contact with the second conductive structure.

Memory device including data lines on multiple device levels

Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems

Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench.

Semiconductor structure formation at differential depths

A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.

Methods of forming apparatuses including air gaps between conductive lines and related apparatuses, memory devices, and electronic systems

Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies.

Growing community of inventors

Boise, ID, United States of America

Naveen Kaushik