Intel Corporation

Nvidia Corporation

Naveen Cherukuri

Theodore Zale Schoenborn

David Stewart Dunning

Sanjay Dabral

Tim Frodsham

Jeffrey R Wilcox

Aaron T Spink

Lakshminarayan Krishnamurty

Gobikrishna Dhanuskodi

Venkatraman Iyer

Phanindra Mannava

Selim Bilgin

Mani Azimi

Robin Tim Frodsham

Vaishali Kulkarni

Adam Hendrickson

Maurice B Steinman

Rahul R Shah

Seh Kwa

Mark Alan Overby

Animesh Mishra

Akhilesh Kumar

Mark Hairgrove

David J O'Brien

Lucien Dunning

Muraleedhara Herur Navada

Vyas Venkataraman

Michael J Tripp

Michael Asbury Woodmansee

Wish Gandhi

Sudeshna Guha

Dwayne Frank Swoboda

Sanjay Darbal

Raymond Wong

Philip John Rogers

Ioannis T Schoinas

Nirmal Raj Saxena

Steven James Heinrich

Allen Jay Baum

Peter C Mills

Anahita Shayesteh

Manan Patel

Dennis W Brzezinski

Liang Yin

Gentaro Hirota

Ching-Tsun Chou

Santanu Chaudhuri

Eduard Roytman

Praveen Joginipally

David Charles Patrick

Sandeep Navada

Saurabh Hukerikar

Phanindra Mannaya

David D Dunning

Paul Racunas

Yiyang Feng

Abhijeet Ghadge

Anuj Rao

Livio B Soares

Livio Soares

Davis S Dunning

Apparatuses, systems, and techniques to generate a trusted execution environment including multiple accelerators. In at least one embodiment, a parallel processing unit (PPU), such as a graphics processing unit (GPU), operates in a secure execution mode including a protect memory region. Furthermore, in an embodiment, a cryptographic key is utilized to protect data during transmission between the accelerators.

Implementing trusted executing environments across multiple processor devices

Secure execution for multiple processor devices using trusted executing environments

Apparatuses, systems, and techniques for handling faults by a direct memory access (DMA) engine. When a DMA engine detects an error associated with an encryption or decryption operation, the DMA engine reports the error to a CPU, which may be executing an untrusted software directing a DMA operation, and the secure processor. The DMA engine waits for clearance from the secure processor before responding to further directions from the potentially untrusted software.

Protecting against resets by untrusted software during cryptographic operations

Apparatuses, systems, and techniques for supporting fairness of multiple context sharing cryptographic hardware. An accelerator circuit includes a copy engine (CE) with AES-GCM hardware configured to perform both encryption and authentication of data transfers for multiple applications or multiple data streams in a single application or belonging to a single user. The CE splits a data transfer of a specified size into a set of partial transfers. The CE sequentially executes the set of partial transfers using a context for a period of time (e.g., a timeslice) for an application. The CE stores in a secure memory for the application one or more data for encryption or decryption (e.g., a hash key, a block counter, etc.) computed from a last partial transfer. The one or more data for encryption or decryption are retrieved and used when data transfers for the application is resumed by the CE.

Fairly utilizing multiple contexts sharing cryptographic hardware

Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.

Error containment for enabling local checkpoint and recovery

The subject application relates to computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) engines. Apparatuses, systems, and techniques are described for computing an authentication tag for a data transfer when the data transfer is scheduled as partial transfers across a specified number of direct memory access (DMA) engines. An orchestration circuit stores partial authentication tags, computed by the DMA engines, and corresponding adjustment exponents during one or more rounds in which the partial transfers are scheduled and processed by the specified number of DMA engines. During a last round, a combined authentication tag can be computed based on the partial authentication tags and the corresponding adjustment exponents stored by the orchestration circuit during the rounds.

Computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) engines

Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.

Link power savings with state retention

Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.

Dynamically modulating link width

An apparatus of an aspect includes a plurality of cores. The plurality of cores are logically grouped into a plurality of clusters. A cluster sharing map-based coherence directory is coupled with the plurality of cores and is to track sharing of data among the plurality of cores. The cluster sharing map-based coherence directory includes a tag array to store corresponding pairs of addresses and cluster identifiers. Each of the addresses is to identify data. Each of the cluster identifiers is to identify one of the clusters. The cluster sharing map-based coherence directory also includes a cluster sharing map array to store cluster sharing maps. Each of the cluster sharing maps corresponds to one of the pairs of addresses and cluster identifiers. Each of the cluster sharing maps is to indicate intra-cluster sharing of data identified by the corresponding address within a cluster identified by the corresponding cluster identifier.

Scalable coherence for multi-core processors

In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.

Region based technique for accurately predicting memory accesses

In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed.

Replacing cache lines in a cache memory based at least in part on cache coherency state information

Growing community of inventors

San Jose, CA, United States of America

Naveen Cherukuri