Unisantis Electronics Singapore Pte. Ltd.

Agency for Science, Technology and Research

Navab Singh

Fujio Masuoka

Hiroki Nakamura

Shintaro Arai

Tomohiko Kudo

Kavitha Devi Buddharaju

Nansheng Shen

Xiang Li

Zhixian Chen

Yisuo Li

Vladimir Bliznetsov

Xinpeng Wang

King-Jien Chui

Yu Jiang

Nozomu Harada

Aashit Ramachandra Kamath

R Ramana Murthy

Shen Nansheng

Rukmani Devi Sayanthan

Rakesh Kumar

Narayanan Balasubramanian

Guo-Qiang Patrick Lo

Ilker Ender Ocak

Julius Ming Lin Tsai

Ajay Agarwal

Ming Lin Julius Tsai

Jaibir Sharma

Srinivas Merugu

Daw Don Cheam

Jae Wung Lee

Vincent Pott

Jae-Wung Lee

Jiaqiang Eldwin Ng

Ieng Kin Lao

A through silicon interposer wafer and method of manufacturing the same. A through silicon interposer wafer having at least one cavity formed therein for MEMS applications and a method of manufacturing the same are provided. The through silicon interposer wafer includes one or more filled silicon vias formed sufficiently proximate to the at least one cavity to provide support for walls of the at least one cavity during subsequent processing of the interposer wafer.

Through silicon interposer wafer and method of manufacturing the same

Various embodiments may provide a device arrangement. The device arrangement may include a substrate including a conductive layer. The device arrangement may further include a microelectromechanical systems (MEMS) device monolithically integrated with the substrate, wherein the MEMS device may be electrically coupled to the conductive layer. A cavity may be defined through the conductive layer for acoustically isolating the MEMS device MEMS device from the substrate. At least one anchor structure may be defined by the conductive layer to support the MEMS device.

Device arrangement

An electromechanical device and method of fabrication thereof comprising: providing a first wafer with a circuit arrangement on a first surface thereof and a first electrode on a second surface thereof; forming first and second via structures from the first surface to the second surface of the first wafer, said first via electrically connecting the first electrode with the circuit arrangement; providing a second wafer with a suspended structure on a first surface thereof; forming a second electrode on the suspended structure; forming an interconnect structure on the first surface of the second wafer that electrically connects with the second electrode; bonding the first wafer to the second wafer with the second surface of the first wafer facing the first surface of the second wafer, with the second via structure electrically connecting the circuit arrangement to the interconnect structure, and the first and second electrodes forming a capacitive structure.

Electromechanical device including a suspended structure and method of fabricating the same

A method for thin film encapsulation (TFE) of a microelectromechanical system (MEMS) device, including providing a substrate; forming a MEMS device on the substrate; forming one or more etching channels adjacent to the MEMS device; providing one or more cavities below the MEMS device; and forming one or more cavities above the MEMS device.

Method for thin film encapsulation (TFE) of a microelectromechanical system (MEMS) device and the MEMS device encapsulated thereof

A memory cell and a method of manufacturing a memory cell are provided. The memory cell includes a substrate; at least one first electrode disposed above the substrate; at least one second electrode disposed above the at least one first electrode; a moveable electrode disposed between the at least one first electrode and the at least one second electrode; wherein the moveable electrode is configured to move between the at least one first electrode and the at least one second electrode; wherein the moveable electrode comprises metal.

Memory cell and method of manufacturing a memory cell

The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.

Surrounding gate transistor (SGT) structure

According to embodiments of the present invention, a resistive memory arrangement is provided. The resistive memory arrangement includes a nanowire, and a resistive memory cell including a resistive layer including a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire, and a conductive layer arranged on at least a part of the resistive layer. According to further embodiments of the present invention, a method of forming a resistive memory arrangement is also provided.

Resistive memory arrangement and a method of forming the same

In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.

Method for producing a semiconductor device and semiconductor device

A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes.

Method for producing semiconductor device and semiconductor device

Embodiments provide a switching device. The switching device includes a substrate, which includes a contact region. The switching device further includes a vertical layer arrangement extending from the substrate next to the contact region. The vertical layer arrangement includes a control layer. The switching device further includes a freestanding silicon cantilever extending vertically from the contact region.

Switching device and a method for forming a switching device

The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.

Surround gate CMOS semiconductor device

A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.

Semiconductor device and production method thereof

A semiconductor device includes a first insulating film formed between a gate electrode and a first flat semiconductor layer, and a sidewall-shaped second insulating film formed to surround an upper sidewall of a first columnar silicon layer while contacting an upper surface of the gate electrode and to surround a sidewall of the gate electrode and the first insulating film. The semiconductor device further includes a metal-semiconductor compound formed on each of an upper surface of a first semiconductor layer of the second conductive type formed in the entirety or the upper portion of the first flat semiconductor layer, and an upper surface of the second semiconductor layer of the second conductive type formed in the upper portion of the first columnar semiconductor layer.

Growing community of inventors

Singapore, Singapore

Navab Singh