Intel Corporation

Tahoe Research, Ltd.

Nausheen Ansari

Arthur Jeremy Runyan

Richmond Hicks

Narayan Biswal

Seh Kwa

Ziv Kabiry

Gal Yedidia

Abhishek R Appu

Joydeep Ray

Srikanth Kambhatla

Sang-Hee Lee

Zhiming Zhuang

Robert J Johnston

Gary K Smith

Todd M Witter

Gary Smith

Nobuyuki Suzuki

Satyanarayana Avadhanam

Paul S Diefenbaugh

Scott R Janus

Changliang Wang

Nilesh V Shah

Ya-Ti Peng

Keith W Rowe

Wen-Fu Kao

Vishal Ravindra Sinha

Atsuo Kuwahara

Jason Daniel Tanner

Stanley J Baran

Lakshminarayana Pappu

Sameer Kp

Jong Dae Oh

Atthar H Mohammed

Hiu-Fai R Chan

Kathy Bui

Yifan Li

Aaron Steyskal

Howard L Heck

Kunjal ShyamKumar Parikh

Karthi R Vadivelu

Abdul Rahman Ismail

Prakash K Radhakrishnan

Roland P Wooster

Amit Kumar Srivastava

Arvind S Tomar

Perazhi Sameer Kalathil

Gaurav Sutaria

Kevin W Krueger

Shah Shah

Embodiments relate to a controller subsystem that includes a virtual reality (VR) subsystem to: identify data received from a peripheral device as related to an audio/visual (A/V) function of the peripheral device; direct, based on the identification that the data is related to the A/V function of the peripheral device, the data to be stored in a memory subsystem of the controller subsystem; and facilitate transmission of an indication of a storage location of the data in the memory subsystem to a host system that is communicatively coupled with the controller subsystem. The controller subsystem further includes a graphics engine to: identify, in a message received from the host system based on the transmission of the indication of the storage location of the data, instructions related to rendering the data; and generate, based on the data received from the peripheral device, rendered data. Other embodiments may be described and claimed.

Low latency communication path for audio/visual (A/V) applications

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

High speed interconnect symbol stream forward error-correction

An apparatus comprising circuitry to buffer video data; and a DisplayPort Transmitter to communicate the video data to a DisplayPort Receiver via a virtual channel through at least one intermediate device between the DisplayPort Transmitter and the DisplayPort Receiver, wherein the virtual channel comprises a unidirectional Main-Link and a bidirectional auxiliary channel (AUX_CH); and communicate a power down signal over the Main-Link to the at least one intermediate device and the DisplayPort Receiver in conjunction with turning off the Main-Link to place the at least one intermediate device and the DisplayPort Receiver in respective low power states.

Advanced link power management for displayport

Disclosed herein are techniques to coordinate power management between a platform and a panel. Provided are apparatuses, techniques, and circuitry to determine whether to initiate power management features in a panel and send a signal from a platform to the panel including an indication that no frame updates are expected and power management functions can be initiated.

Co-existence of full frame and partial frame idle image updates

Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.

Glare and occluded view compensation for automotive and other applications

One embodiment provides a video transport system. The video transport system includes graphics processing circuitry to generate a video transport unit (TU) corresponding to a scan line of a first video frame that is unchanged from a second video frame, wherein the video TU includes a control sequence and an unchanged data payload corresponding to a defined number of pixels of the scan line of the first video frame. The video transport system of this embodiment also includes source tunneling bridge circuitry to generate a bus TU based on the video TU; the source tunneling bridge circuitry to parse the control sequence or the unchanged data payload of the video TU, and to generate the bus TU having a header that includes a field to identify the defined number of pixels of the unchanged data payload, and to eliminate, in whole or in part, the unchanged data payload in the bus TU.

Link bandwidth improvement techniques

Systems, apparatuses and methods may include a source device that generates a scene change notification in response to a movement of a camera, modifies an encoding scheme associated with the video content captured by the camera in response to the scene change notification, identifies a full-frame difference threshold, wherein scene analysis information includes frame difference data, and compares the frame difference data to an intermediate threshold that is less than the full-frame difference threshold, wherein the scene change notification is generated when the frame difference data exceeds the intermediate threshold. A sink device may obtain transport quality data associated with video content, modify an output parameter of a display based on the transport quality data, determine a view perspective of a still image containing a plurality of image slices, retrieve only a subset of the plurality of image slices based on the view perspective and decode the retrieved subset.

Technology to accelerate scene change detection and achieve adaptive content display

In one embodiment, an apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link.

Display link power management using in-band low-frequency periodic signaling

Methods, apparatus, systems, and articles of manufacture are disclosed to reduce display connection latency. An example apparatus includes interface circuitry to: detect when a display is plugged into a port; and notify processor circuitry of the detection. In response to the notification, the processor circuitry of the example apparatus moves discrete circuitry into a high power state. The example apparatus also includes discrete circuitry to, while in the high power state, identify the display.

Methods and apparatus to reduce display connection latency

Technology for a display controller is described. The display controller can detect a frame update when the display controller is in a dynamic sleep state. The display controller can wake up from the dynamic sleep state and enter a selective update state at a programmed vertical blanking interrupt (VBI) that precedes an actual VBI. The display controller can perform a scan-out with a display panel during the selective update state. The display controller can return to the dynamic sleep state in a same time frame after the scan-out is completed. The display controller can exclude timing logic to send a VBI at every time frame to the display panel to maintain time synchronization between the display controller and the display panel.

Dynamic sleep for a display panel

An apparatus comprising an interface to receive a video signal transmitted by a video source device to a first port of a plurality of ports of a display; and a controller comprising circuitry, the controller to responsive to a detection that the video source device is to enter a standby mode, cause the display to enter a low power state; and upon waking from the low power state, scan the first port of the plurality of ports for a communication from the video source device and quiesce scanning of the remaining one or more ports of the plurality of ports of the display.

Enhanced display wakeup utilizing fast port scanning

The present disclosure is directed to systems and methods of maintaining source device to sink device synchronization in systems in which the source device enters a Panel Self-Refresh (PSR/PSR2) mode and the sink device enables adaptive synchronization with the source device. To maintain synchronization, in some instances the source device and the sink device may maintain synchronization contemporaneous with at least a portion of the PSR/PSR2 operating mode. To maintain synchronization, in some instances, a high-bandwidth communications link may be maintained between the source device and the sink device. In some instances, synchronization between the source device and the sink device may be interrupted upon the source device entering the PSR/PSR2 operating mode and may be re-established upon the source device exiting the PSR/PSR2 operating mode.

Combined panel self-refresh (PSR) and adaptive synchronization systems and methods

In some examples, a transport agnostic source includes a streaming device to stream video on diverse transport topologies including isochronous and non-isochronous transports. In some examples, a transport agnostic sink includes a receiving device to receive streamed video from diverse transport topologies including isochronous and non-isochronous transports.

Streaming on diverse transports

Growing community of inventors

Folsom, CA, United States of America

Nausheen Ansari