Varian Semiconductor Equipment Associates, Inc.

Applied Materials, Inc.

Naushad K Variam

Johannes M Van Meer

Sony Varghese

Min Gyu Sung

Jae Young Lee

Yan Zhang

Steven Raymond Walther

Sandeep Mehta

John J Hautala

Tristan Yonghui Ma

Armin Saeedi Vahdat

Ukyo Jeong

Christopher Dennis Bencher

Morgan Evans

Anthony Renau

Benjamin Colombeau

Adam Brand

Mandar Balasaheb Pandit

Andrew Michael Waite

Jun Seok Lee

Sankuei Lin

Tassie Andersen

Baonian Guo

Nilay A Pradhan

A method of processing a workpiece that will include a backside power delivery network is disclosed. The method includes forming a CMP marker layer in the workpiece at the depth to which the workpiece is to be thinned. This CMP marker layer, which may be a boron-rich layer, serves to slow the chemical-mechanical planarization (CMP) process. To minimize the diffusion of boron in this boron-rich layer, the boron-rich layer is sandwiched by implants of a first species of ions, where this first species of ions serves to slow the diffusion of the boron. In certain embodiments, carbon is used as the first species of ions.

Carbon and boron implantation for backside chemical mechanical planarization control

Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a well by directing a first ion species into a substrate of a device, forming a plurality of alternating first and second layers over the well, and forming a dummy gate and a spacer over the plurality of alternating first and second layers. The method may further include removing a portion of the plurality of alternating first and second layers to expose an upper surface of the well, forming a punch through stopper in the well by directing a second ion species into the exposed upper surface of the well, etching the plurality of nanosheets to laterally recess the second layers relative to the first layers, and forming an inner spacer along the first and second layers.

Ion implantation process to form punch through stopper

A method for forming a nanosheet device. The method may include providing a heterostructure device stack above a semiconductor substrate. The method may include patterning the heterostructure device stack to define a dummy gate region, and before forming a source drain recess adjacent the dummy gate region, selectively removing a first set of sacrificial layers of the heterostructure device stack within the dummy gate region.

Three dimensional device formation using early removal of sacrificial heterostructure layer

A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.

Bottom implant and airgap isolation for nanosheet semiconductor devices

Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.

Semiconductor device cavity formation using directional deposition

Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.

Wordline contact formation in NAND devices

A method may include providing a substrate, the substrate comprising a substrate base and a patterning stack, disposed on the substrate base. The substrate may include first linear structures in the patterning stack, the first linear structures being elongated along a first direction; and second linear structures in the patterning stack, the second linear structures being elongated along a second direction, the second direction forming a non-zero angle with respect to the first direction. The method may also include selectively forming a set of sidewall spacers on one set of sidewalls of the second linear structures.

Dynamic random access device including two-dimensional array of fin structures

Methods herein may include forming a gate dielectric within a set of trenches in a stack of layers. A first work function (WF) metal may be formed atop the gate dielectric, and a capping layer may be formed over the first WF metal using an angled ion implant deposition, the capping layer extending across the trenches.

Replacement gate formation with angled etch and deposition

A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.

Structure and method of forming fin device having improved fin liner

The present disclosure is directed to structures and processing for three-dimensional transistor devices. In some approaches, a method may include providing a plurality of fin structures formed from a substrate, the plurality of fin structures disposed subjacent to a hard mask layer, and directing angled ions at the plurality of fin structures. The angled ions may form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, wherein the angled ions etch the plurality of fin structures to form a stack of isolated nanowires within the plurality of fin structures. The method may further include removing the hard mask layer, and forming a stopping layer over the stack of isolated nanowires.

Gate devices and methods of formation using angled ions

A method of forming a semiconductor device. The method may include providing a device structure, where the device structure comprises a masked portion and a cut portion. The masked portion may comprise a mask covering at least one semiconductor fin of a fin array, and the cut portion may comprise a trench, where the trench exposes a semiconductor fin region of the fin array. The method may further include providing an exposure of the trench to oxidizing ions, the oxidizing ions to transform a semiconductor material into an oxide.

Method of forming transistor device having fin cut regions

Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include recessing the STI material to reveal an upper portion of the plurality of fins, implanting the semiconductor device, and forming a capping layer over the plurality of fins and the STI material. The method may further include removing a first fin section of the plurality of fins and a first portion of the capping layer, wherein a second fin section of the plurality of fins remains following removal of the first fin section.

Fin damage reduction during punch through implantation of FinFET device

Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer.

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Marblehead, MA, United States of America

Naushad K Variam