Renesas Electronics Corporation

Natsuo Yamaguchi

Satoshi Eguchi

Yuya Abiko

Tetsuya Iida

Akio Ichimura

Shoji Yoshida

Takashi Takeuchi

Norio Ishitsuka

Atsushi Maeda

Hiroshi Ishida

Yasuhiro Kimura

Tetsuya Uchida

Daisuke Taniguchi

Shigeaki Saito

Minoru Abiko

Takehiko Kijima

In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PRare formed on the sides of an n-type column NCadjacent to a p-type column region PC. In this configuration, the p-type semiconductor region PRis formed from the upper end of the n-type column region NCto about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PRand the p-type column region PC

Semiconductor device and method of manufacturing the same

Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).

Semiconductor device and method of manufacturing the semiconductor device

In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Semiconductor device and manufacturing method for the semiconductor device

A technique that makes it possible to suppress a crystal defect produced in an active area and thereby reduce the fraction defective of semiconductor devices is provided. A first embodiment relates to the planar configuration of SRAM. One of the features of the first embodiment is as illustrated in FIG.. That is, on the precondition that the active areas in n-channel MISFET formation regions are all configured in the isolated structure: the width of the terminal sections is made larger than the width of the central parts of the active areas. For example, the terminal sections are formed in an L shape.

Semiconductor device with suppressed crystal defects in active areas

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Ibaraki, Japan

Natsuo Yamaguchi