Mitsubishi Denki Kabushiki Kaisha

Genusion, Inc.

Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Engineering Corp.

Natsuo Ajika

Hideaki Arima

Atsushi Hachisuka

Makoto Ohi

Shoji Shukuri

Hiroshi Onoda

Masaaki Mihara

Moriyoshi Nakashima

Taku Ogura

Yuichi Kunori

Atsushi Fukumoto

Satoshi Shimizu

Tomonori Okudaira

Kazuyuki Sugahara

Kaoru Motonami

Yasushi Matsui

Yasuo Yamaguchi

Takeshi Nakayama

Masahiro Shimizu

Shinichi Kobayashi

Yoshiki Kawajiri

Yasushi Terada

Yoshikazu Miyawaki

Tomoshi Futatsuya

Kiyohiko Sakakibara

Takehisa Yamaguchi

Takahiro Onakado

Tsuyoshi Yamano

Kazuo Kobayashi

Toshiaki Iwamatsu

Takashi Ipposhi

Yoshinori Okumura

Toshiaki Ogawa

Koji Eguchi

Takahiro Oonakado

Atsushi Ohba

Shinichi Satoh

Hirofumi Shinohara

Takahisa Eimori

Akinori Matsuo

Yasuyoshi Itoh

Kiyoto Watabe

Osamu Sakamoto

Haruo Furuta

Shuuichi Ueno

Yuichi Nakashima

Naho Nishioka

Masahiro Hatanaka

Tatsuya Shiromoto

A nonvolatile semiconductor memory device is provided which includes: a P-type memory cell transistor having a source, a drain, a gate, and a charge storage layer; and a control circuit which, in a case where the P-type memory cell transistor has its threshold greater than or equal to a first value (Vr) and less than or equal to a second value (Vrd), carries out a program operation of injecting electrons into the charge storage layer.

Read disturb control in a nonvolatile semiconductor memory device having P-type memory cell transistor

According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one corresponding bit line of the plurality of bit lines and the second terminal being connected to one corresponding source line of the plurality of source lines.

Nonvolatile semiconductor memory device

A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg&#x3e;Vsub&#x3e;Vs&#x3e;Vd is satisfied, Vg&#x2212;Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub&#x2212;Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

Nonvolatile semiconductor memory

A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

Non-volatile semiconductor memory device and manufacturing method thereof

Non-volatile semiconductor memory device

According to an one aspect of the present invention, it is provided a non-volatile semiconductor memory device comprising: a first N type well; a plurality of P type non-volatile memory cells arranged in matrix and formed in the N type well; a plurality of sub-bit lines, each of the sub-bit lines being connected to drains of the P type non-volatile memory cells in a respective one of columns of the matrix; a first P type well; and a plurality of N type selection transistors, each of the selection transistors selectively connecting a respective one of sub-bit lines to a corresponding one of main bit lines.

Non-volatile semiconductor memory device comprising capacitive coupling program inhibit circuitry

A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.

Interposer, semiconductor chip mounted sub-board, and semiconductor package

A nonvolatile semiconductor memory device includes a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

Nonvolatile semiconductor memory device and usage method thereof

The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

A semiconductor chip mounted interposer () is configured by executing wire bonding between a semiconductor chip () and an interposer (), in which terminals () that connect to terminals () of the chip () and separate terminals () are formed, on the upper face of the interposer (). A semiconductor chip () is mounted to the top face of a package substrate (), the interposer () is adhered to the upper portion of the chip (), and wire bonding is executed between the terminals () and terminals ('). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.

Semiconductor device package structure

A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg&#x3e;Vsub&#x3e;Vs&#x3e;Vd is satisfied, Vg&#x2212;Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub&#x2212;Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

Nonvolatile semiconductor storage device and method for writing therein

Growing community of inventors

Hyogo, Japan

Natsuo Ajika