Mitsubishi Denki Kabushiki Kaisha

Natsuko Matsuo

Minobu Yazawa

Shiro Hosotani

A block to raster converting circuit which is adaptable to all formats with a single circuit is realized. Macro-block data is mapped into a frame memory ( ) on the basis of a particular format whose data size (X) in the horizontal direction provides a max condition. When writing, for each macro-block row (MBRi), the address of the first data in the initial macro-block (IMBi) is specified, on the basis of which address the column and row addresses are regularly switched according to the data array in the macro-block (MB). When reading, for each macro-block row (MBRi), the address of the initial data is specified, on the basis of which address the row address is switched every time data in each horizontal line in the macro-block row (MBRi) has been read and every time data at a turn of the column address in the frame memory ( ) has been read. The column address is sequentially switched.

Semiconductor integrated circuit for converting macro-block data into raster data which is adaptable to various formats

A decoder for converting packet data into raster data is provided. The packet data includes data about a picture-compressed video signal and data about a picture format including a picture rate. The decoder comprising a first processing means, second processing means and a storage means. The first processing means converts the packet data into intermediate data such that picture compression is eliminated from the picture-compressed video signal and outputs the intermediate data. The second processing means receives the intermediate data from the first processing means and processes the intermediate data to output raster data for one frame at a frame frequency. The storage means stores the intermediate data for processing the intermediate data in the second processing means. The second processing means writes the intermediate data into the storage means at a frequency related to the picture rate and reads the raster data for one frame from the storage means at the frequency equal to the frame frequency.

Displaying format converter for digitally encoded video signal data

Two input data X (7), Y (7), . . . , X (0), Y (0) are input to a plurality of full adders, and an overflow/underflow signal of each full adder is input to a full adder of a higher level. An overflow/underflow signal Co of the full adder of the most significant bit and data Y (7) are applied to an EXOR gate to obtain an exclusive OR. According to an output signal of the EXOR gate, an added output of each full adder or data Y (7) is selected by a selector, whereby a straight binary signal is output.

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Tokyo, Japan

Natsuko Matsuo