Nec Corporation

Elpida Memory, Inc.

Nitto Boseki Co., Ltd.

Nec Electronics Corporation

Shinshu University

Natsuki Sato

Isamu Asano

Hideki Ishihara

Takanori Saeki

Wolodymyr Czubatyj

Ryo Kojima

Yoshiro Sato

Akiyoshi Seko

Masayuki Wakabayashi

Tyler A Lowrey

Toshiyuki Hirota

Stephen J Hudgens

Guy Charles Wicker

Yukio Fuji

Tsutomu Hayakawa

Kenta Noda

Jeffrey P Fournier

Mika Kuroiwa

Masatoshi Nakatsuji

Kiyotaka Fujita

Kaduho Ashizawa

Provided are a pretreatment method for detecting the number of cells containing Ki-67 protein-positive nuclei using Ki-67 antibody; a method for the detection; a kit to be used in the detection method; and determination of a therapy regimen using the aforesaid method. Attempts were made to activate Ki-67 antigen with the use of an enzyme having been considered as inappropriate for the activation thereof. By pretreating a sample with an enzyme not recognizing the epitope of MIB-1 (a rare cutter enzyme), the antigen activation of Ki-67 antigen was enhanced, while enhancing the antigenicity of other antigens including a cytokeratin too. As a result, a method for more objectively and more universally quantifying Ki-67-positive cells at higher reproducibility, said method comprising isolating cell nuclei from an FFPE section while enhancing the antigenicity and performing a reaction between Ki-67 protein, i.e., the target, existing in the cell nuclei with a fluorescently labeled antibody, has been completed.

Method for isolating cell nuclei having enhanced antigenicity from fixed cells or FFPE tissue section, and antigen activator and kit therefor

The present invention addresses the problem of providing a novel method for classifying cancer cells by an analysis method in which measurement of the activity of two types of protein kinase is used. Cancer cells are newly classified and drug sensitivity is predicted on the basis of the ratio of the activity of two types of protein kinase derived from the same sample.

Method for determining drug-sensitive human cell lines by analysis method in which measurement of activity of two types of protein kinase is used

Disclosed is a test instrument for measuring an analyte in a liquid sample by a noble metal colloid aggregation measurement method. The test instrument involves a reaction chamber in which at least the liquid sample is to be reacted with a reagent, wherein the reagent is adhered on at least a part of a surface constituting the reaction chamber in a dried state, and the reagent enables the measurement of the analyte by a noble metal colloid aggregation measurement method. The test instrument additionally involves a supply section for supplying the liquid sample and a flow path for delivering the liquid sample that has been supplied to the supply section to the reaction chamber, wherein the liquid sample that has been supplied to the supply section is delivered to the reaction chamber through the flow path to cause the liquid sample to be brought into contact with the reagent that has been adhered in a dried state, thereby producing a difference in pressure between the supply section and the reaction chamber for the purpose of dispersing the reagent in the liquid sample. When the test instrument is used, the measurement based on an absorbance at a visible region can be achieved, the analyte can be measured accurately within a short time, and the measurement suitable for a POCT field can be achieved.

Test instrument for measuring analyte in sample by an aggregation assay using a metal colloid and using a reagent attached in a dry state in a reaction chamber, and method for measuring analyte using same

In the case of assaying the level of complex AB in a sample which likely contains the complex AB composed of substance A with another substance B, the complex is assayed by the competitive homogeneous assay method with the use of reagents including a reagent containing partner C specifically binding to substance A, a reagent containing partner D specifically binding to substance B, a reagent containing fine particles carrying substance A or an analog thereof and substance B or an analog thereof, and a reagent containing partner C specifically binding to substance A and partner D specifically binding to substance B. Thus, the complex in the sample can be easily assayed. The above method is applicable to general-purpose biochemical automatic analyzers.

Method of assaying complex and kit to be used therefor

A nonvolatile memory device () is provided with a semiconductor substrate, a plurality of active regions () formed on the semiconductor substrate and extending in a band, a plurality of select active elements () formed in the active regions () and having a first impurity diffusion region and a second impurity diffusion region, a plurality of first electrodes () electrically connected to the first impurity diffusion region, a variable resistance layer () electrically connected to the first electrodes (), and a plurality of second electrodes electrically connected to the variable resistance layer (). Among the plurality of first electrodes () and the plurality of second electrodes, an array direction of at least one pair of the first electrodes () and the second electrodes that are electrically connected to the same variable resistance layer (), and a direction of extension of the activation regions () are not parallel.

Nonvolatile memory device

An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller.

Method of producing phase change memory device

A phase change memory device is provided in which the area of contact between phase change material and heater electrode is reduced to suppress current required for heating and a phase change region is formed directly on a contact to raise the degree of integration. The device comprises a heater electrode in which the lower part thereof is surrounded by a side wall of a first insulating material and the upper part thereof protruding from the side wall has a sharp configuration covered by a second insulating material except for a part of the tip end thereof, and the exposed tip end is coupled to the phase change material layer.

Phase change memory device and fabrication method thereof

A semiconductor device includes an interlayer insulating film formed on a semiconductor substrate to cover a lower electrode, a side-wall insulating film formed on a side wall of a contact hole formed through the interlayer insulating film to a depth reaching the lower electrode, a heater formed in the interior of the contact hole defined by the side-wall insulating film, and a phase-change film in contact with the top surface of the heater. The heater is in contact with the lower electrode at the bottom surface within the contact hole, and the top surface thereof is located at a lower level than that of the top surface of the side-wall insulating film. The top surface of the heater is located at a lower level than the top surface of the side-wall insulating film by an extent equal to or greater than a thickness of the phase-change film.

Semiconductor device and manufacture method thereof

A non-volatile memory element comprises a bottom electrode; a top electrode; and a recording layercontaining phase change material and a block layerthat can block phase change of the recording layer, provided between the bottom electrodeand the top electrode. The block layeris constituted of material having an electrical resistance that is higher than that of material constituting the recording layer. The block layersuppresses the radiation of heat towards the top electrodeand greatly limits the phase change region when a write current is applied. The result is a high heating efficiency. The top electrodeitself can be used to constitute a bit line, or a separate bit line can be provided.

Electrically rewritable non-volatile memory element and method of manufacturing the same

A phase change memory includes a sidewall insulation film and a heater electrode which are formed in a contact hole formed in an interlayer insulation film on a lower electrode. The heater electrode has a recessed structure. In a recessed area surrounded by the sidewall insulation film, the heater electrode and a phase change film are contacted with each other. A phase change region is formed only in an area contacted with the sidewall insulation film. The sidewall insulation film is an anti-oxidizing insulation film. The phase change region and the heater electrode which are heated to a high temperature upon rewriting are not contacted with the interlayer insulation film as an oxidizing insulation film.

Semiconductor device and method of producing the same

A non-volatile memory element includes a first interlayer insulation layerhaving a first through-hole, a second interlayer insulation layerhaving a second through-holeformed on the first interlayer insulation layer, a bottom electrodeprovided in the first through-hole, recording layercontaining phase change material provided in the second through-hole, a top electrodeprovided on the second interlayer insulation layer, and a thin-film insulation layerformed between the bottom electrodeand the recording layer. In accordance with this invention, the diameter Dof a bottom electrodeburied in a first through-holeis smaller than the diameter Dof a second through-hole, thereby decreasing the thermal capacity of the bottom electrode. Therefore, when a poreis formed by dielectric breakdown in a thin-film insulation layerand the vicinity is used as a heating region, the amount of heat escaping to the bottom electrodeis decreased, resulting in higher heating efficiency.

In a semiconductor device, a phase change layer is formed as a side wall and is therefore reduced in volume. Even if the number of times of rewriting is small, the phase change layer is entirely used as a phase change region. Therefore, the phase change region is not increased in volume even if the number of times of rewriting is increased. Since the volume of the phase change region is not changed, an electric current level required for rewriting is constant. Thus, the semiconductor device having a memory cell capable of carrying out stable rewriting is obtained.

A semiconductor device manufacturing process for forming a semiconductor device having a high density region and a low density region of transistor elements, includes forming a gate oxide film and gate electrodes on a semiconductor substrate surface. Then, a first nitride film is uniformly formed on the gate electrodes, and only the low-density region of the semiconductor device is etched. Then, a second nitride film is uniformly formed, and then an interlayer insulating film is formed. The high-density region is self-aligned using the first nitride film as an etch stopper to form contact holes in the interlayer insulating film, and contact electrodes are formed In the contact holes. The assembly is then annealed by a forming gas to recover an interfacial layer.

Semiconductor device with high- and low-density regions of transistor elements on single semiconductor substrate, and method of manufacturing such semiconductor device

A wiring structure for a semiconductor device comprises a first interlayer insulating film formed on a semiconductor substrate, first level wiring conductors formed on the first interlayer insulating film, a second interlayer insulating film formed to cover the first level wiring conductors and including a SOG film, and a second level wiring conductors formed on the second interlayer insulating film. A first level wiring conductor which is formed in a peripheral zone of a semiconductor chip and which has to have a wide line width, is divided into a plurality of divided wiring conductors having a narrow line width. Alternatively, the first interlayer insulating film in the peripheral zone of the semiconductor chip is etched by a predetermined thickness so that the first level wiring conductor located in the peripheral zone of the semiconductor chip is formed at a level lower than the first interlayer insulating film located in an inside of the semiconductor chip. Therefore, the first level wiring conductor located in the peripheral zone of the semiconductor chip is constituted of a set of the divided wiring conductors having the narrow line width.

Growing community of inventors

Tokyo, Japan

Natsuki Sato