Kabushiki Kaisha Toshiba

Rambus Inc.

Natsuki Kushiyama

Donald C Stark

Tohru Furuyama

Jun Y Kim

Michael Tak-Kei Ching

Kurt T Knorpp

Masaru Koyanagi

Kenji Numata

Katsuki Matsudera

Satoru Takase

Yukihiro Urakawa

Toshiki Hisada

Takahiko Hara

Kaoru Nakagawa

Kazuhide Yoneya

Shigeo Ohshima

Kiyofumi Sakurai

Shigeaki Iwasa

Hiroyuki Noji

Masao Kudou

Ryubi Okuda

Tadashi Onizawa

According to one embodiment, an output driver which outputs an output signal to a transmission line, the output driver includes a pre-driver and a main driver. The pre-driver changes the duty ratio of a first drive signal and the duty ratio of a second drive signal to a plurality of patterns in accordance with a control signal. The main driver connects in series a first driver driven by the first drive signal and a second driver driven by the second drive signal. The main driver outputs the output signal to the transmission line from a connection node of the first and second drivers.

Output driver to drive semiconductor device and memory system

According to one embodiment, a semiconductor device is provided with first to third circuits. The first circuit generates first information that indicates a corresponding relationship between a period of a reference clock and a delay amount per delay element. The second circuit generates second information that indicates the number of stages of delay elements corresponding to a set phase difference based on the first information. The third circuit generates a delayed clock by delaying the reference clock just a delay amount of stages of the delay elements indicating the second information.

DLL circuit and semiconductor device

A semiconductor integrated circuit according to an example of the present invention includes a chip substrate, first and second switches arranged on the chip substrate in which ON/OFF of an electrical signal path is directly controlled by an optical signal, a first light shielding layer arranged above the chip substrate, an optical waveguide layer arranged on the first light shielding layer, a second light shielding layer arranged on the optical waveguide layer, a reflecting plate arranged in the optical waveguide layer to change an advancing direction of the optical signal, and means for leading the optical signal to the first and second switches from an inside of the optical waveguide layer. The first and second light shielding layers reflect the optical signal, and the optical waveguide layer transmits the optical signal radially.

Semiconductor integrated circuit

A semiconductor integrated circuit has a cell array, a redundancy cell capable of replacing a defective cell, a redundancy control circuit, a plurality of first fuses, a plurality of second fuses, a plurality of third fuses, a first shift register configured to hold states of the plurality of first fuses, a second shift register configured to be connected in cascade to the first shift register and to hold states of the plurality of second fuses, a third shift register configured to be connected to the first and second shift registers in cascade and to hold states of the plurality of third fuses, a CRC remainder calculator configured to sequentially input information held by the first to third shift registers to a CRC generating equation to calculate a remainder obtained by division, and a CRC determination part that outputs information indicative of whether the first to third fuses are correctly programmed.

Semiconductor integrated circuit and the same checking method

Embodiments of present invention provide a circuit including a voltage regulator, a phase frequency detector, a charge pump, a low pass filter a control-voltage generating circuit and a voltage controlled oscillator. In a first mode of operation the voltage controlled oscillator produces an output clock in accordance with a control voltage produced from the control-voltage generating circuit and the output voltage of the voltage regulator. In a second mode of operation, the voltage controlled oscillator produces an output clock in accordance with a control voltage from the low pass filter and the output voltage of the voltage regulator.

Phase locked loop circuit having regulator

A resistance-change-type fuse circuit has a plurality of polysilicon fuses which are made of polysilicon and causes irreversible change in resistance by flowing a current; a plurality of programming transistors which are provided corresponding to the plurality of fuses, each programming transistor switching whether to flow the current through the corresponding fuse to cause change in resistance with respect to the polysilicon fuses, a dummy fuse group including a plurality of dummy fuses having the same electrical properties as that of the polysilicon fuses, each dummy fuse having 1/n (n is an integer equal to or more than 1) times a resistance of the polysilicon fuses, a dummy transistor circuit which has at least one of dummy transistor having 1/n times a conductance of the programming transistors, a gate and a drain of the dummy transistor being connected to each other, and a current mirror circuit including the programming transistor and the dummy transistor, the current mirror circuit causing each polysilicon fuse to flow n times the current flowing through the dummy fuse group.

Resistance-change-type fuse circuit

A data sampling circuit has a receiver which receives an embedded clock obtained by multiplexing a clock signal and data, a phase comparator which outputs a phase difference signal by performing a phase comparison between the embedded clock and a first reference clock signal, a phase interpolator which adjusts a phase of the first reference clock signal and generates a second reference clock signal having a phase different from the phase of the first reference clock signal by 90&#xb0;, based on the phase difference signal, a feedback controller which conforms the phase of the first reference clock signal with the phase of the embedded clock by feedback control using the phase comparator and the phase interpolator, a sampling controller which performs phase interpolation of the second reference clock signal at higher speed than the feedback control of the first feedback loop based on the phase difference signal, and a sampling circuit which samples the embedded clock received by the receiver in synchronization with the second reference clock signal obtained by phase interpolation of the sampling controller.

Data sampling circuit and semiconductor integrated circuit

A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a first delay of the first delay clock; a second register registering a value of a second delay of the second delay clock; a clock supplying circuit supplying a clock signal to the first and second delay circuits; a phase comparator detecting a phase difference between the first and second delay clocks; and a built-in test circuit configured to control the first and second registers so that the value of the first delay can be registered in the first register and the value of the second delay can be registered in the second register.

Semiconductor integrated circuit and method for testing a semiconductor integrated circuit

A driver circuit disclosed herein comprises a first inverter which comprises: a first transistor which is connected between a first power supply with a first voltage and a first output node; a second transistor which is connected between the first output node and a second power supply with a second voltage; and a voltage maintaining circuit which is provided between the second power supply and the second transistor and which maintains a voltage of the first output node in the vicinity of a threshold voltage of a transistor which is connected to the first output node even when the second transistor is turned on.

Driver circuit and system including driver circuit

An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output currentriver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

Impedance controlled output driver

An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

Charge compensation control circuit and method for use with output driver

A semiconductor IC device includes a pad, an input receiver, an input receiver control circuit, an output driver, an output driver control circuit, an input control clock signal line, a reference potential line, an output control clock signal line, a first power supply line, and a second power supply line. The input receiver, the input receiver control circuit, the output driver control circuit, the input control clock signal line, the reference potential line, the output control clock signal line, and the first power supply line are arranged on one side of the pad, while the output driver and the second power supply line are arranged on the other side of the pad.

Semiconductor integrated circuit device and semiconductor device system

A semiconductor integrated circuit includes first and second MOS transistors and a capacitor. The first MOS transistor has a drain connected to an output terminal, a gate and a source. The second MOS transistor has a gate, a drain connected to the source of the first MOS transistor and a source and has the same conductivity type as the first MOS transistor. The capacitor has one electrode connected to the gate of the first MOS transistor and the other electrode connected to a node whose potential changes in a complementary fashion with respect to the drain potential of the first MOS transistor and functions to cancel out an influence, caused by the coupling of a mirror capacitor which exists between the gate and drain of the first MOS transistor, affecting the gate potential of the first MOS transistor.

Semiconductor integrated circuit having output buffer

A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.

Growing community of inventors

Kawasaki, Japan

Natsuki Kushiyama