Toshiba Memory Corporation

Kioxia Corporation

Kabushiki Kaisha Toshiba

Natsuki Fukuda

Atsushi Oga

Takeshi Yamaguchi

Mutsumi Okajima

Toshiharu Tanaka

Takeshi Takagi

Hiroyuki Ode

Satoshi Nagashima

Tadashi Iguchi

Masanori Komura

Kazuhiro Matsuo

Shinji Mori

Kenichiro Toratani

Masaki Yamato

Yuta Saito

Hiroyuki Yamashita

Kota Takahashi

Tomoki Ishimaru

Yuta Kamiya

Tetsu Morooka

Takashi Kurusu

Ha Hoang

Ryota Narasaki

Hideaki Harakawa

Takafumi Ochiai

Junichi Kaneyama

Moto Yabuki

Shoji Honda

Noritaka Ishihara

A semiconductor storage device includes a substrate having a memory region and a hook-up region arranged in a first direction and memory structures arranged in a second direction. The memory structures include conductive layers arranged in a third direction and extending in the first direction over the memory region and the hook-up region and contact electrodes provided in the hook-up region and extending in the third direction to have an outer peripheral surface surrounded, each contact electrode being connected to any of the conductive layers. The hook-up region includes a first region, with a first contact electrode and a second contact electrode, and a second region, with a third contact electrode and a fourth contact electrode. In the third direction, a first average length of the first and second electrodes is equal to a second average length of the third and fourth contact electrodes.

Semiconductor storage device

A semiconductor storage device includes a first conductive layer that extends in a first direction; a second conductive layer that extends in the first direction and is arranged with the first conductive layer in a second direction; a first insulating layer that is provided between the first conductive layer and the second conductive layer; a semiconductor layer that extends in the second direction and faces the first conductive layer, the second conductive layer, and the first insulating layer in a third direction; a first charge storage layer that is provided between the first conductive layer and the semiconductor layer; a second charge storage layer that is provided between the second conductive layer and the semiconductor layer; a first high dielectric constant layer that is provided between the first conductive layer and the first charge storage layer; and a second high dielectric constant layer provided between the second conductive layer and the second charge storage layer. At least a portion of the first charge storage layer faces the second charge storage layer without the second high dielectric constant layer being interposed between the portion of the first charge storage layer and the second charge storage layer in the second direction.

A semiconductor memory device includes a substrate, conductive layers arranged in a first direction and extend in a second direction, a semiconductor layer extending in the first direction and opposed to the conductive layers, and n contact electrode regions arranged in a third direction. The n is a power of 2. The contact electrode region includes contact electrodes arranged in the second direction. The conductive layers include a first conductive layer and a second conductive layer that is an n-th conductive layer counted from the first conductive layer. The contact electrodes include a first contact electrode connected to the first conductive layer, a second contact electrode connected to the second conductive layer, and a third contact electrode disposed between them. The first contact electrode, the second contact electrode, and the third contact electrode are arranged in the second direction or the third direction.

Semiconductor memory device

A semiconductor memory device includes a first chip and a second chip. The first chip includes a semiconductor substrate and a plurality of transistors disposed on a surface of the semiconductor substrate. The second chip includes a plurality of first conductive layers, a plurality of first semiconductor layers, and a plurality of memory cells disposed in intersection portions of the plurality of first conductive layers and the plurality of first semiconductor layers. The second chip includes a second semiconductor layer farther from the semiconductor substrate than the plurality of first conductive layers. The second semiconductor layer is connected to the plurality of first semiconductor layers and a first insulating layer that includes a part farther from the semiconductor substrate than a surface on a side opposite to the semiconductor substrate of the second semiconductor layer and a part closer to the semiconductor substrate than the surface.

According to an embodiment, a semiconductor memory device includes: a first stacked body including a first semiconductor layer, a first memory film, a second semiconductor layer and a first insulating layer; a joining member provided on the first semiconductor layer, the second semiconductor layer, and the first insulating layer; a first layer provided above the joining member and covering the first semiconductor layer and the first memory film; a second layer provided above the joining member, located away from the first layer as viewed in a second direction perpendicular to the first direction, and covering the second semiconductor layer and the second memory film; a second stacked body including a third semiconductor layer, a fourth semiconductor layer, a fourth memory film and a second insulating layer.

According to one embodiment, a semiconductor storage device includes a first charge storage part, a first insulating part, a second charge storage part, a second insulating part, a first select transistor, and a hollow part. The first charge storage part is at a first position separated from a surface of a substrate by a first distance in a third direction. The first select transistor is at a second position separated from the surface of the substrate by a second distance in the third direction. The second distance is greater than the first distance. The hollow part is up to a third position in the third direction separated from the surface of the substrate by a third distance in the third direction. The third distance is greater than or equal to the first distance and shorter than or equal to the second distance.

A semiconductor memory device according to an embodiment comprises: a semiconductor substrate extending in a first direction and a second direction, the first and second directions intersecting each other; a first wiring line disposed above the semiconductor substrate and extending in the first direction; a second wiring line disposed above the semiconductor substrate and extending in a third direction, the third direction intersecting the first direction and the second direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a first insulating film disposed aligned with the second wiring line in the first direction; a first film disposed between the first wiring line and the first insulating film; and a second film disposed between the first insulating film and the first film and configured from a material different from that of the first film.

Semiconductor memory device and method of manufacturing the same

A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.

Semiconductor device and method of manufacturing the same

A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.

A semiconductor memory device according to an embodiment includes: a semiconductor substrate which extends in first and second directions that intersect each other; a plurality of first wiring lines which are arranged in a third direction that intersects the first direction and the second direction, and which extend in the first direction; a plurality of second wiring lines which are arranged in the first direction and extend in the third direction; and a plurality of memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells having a first film whose resistance changes electrically, a thickness in the second direction of the first film changing with respect to a change of position in the third direction, and the first films of two of the memory cells adjacent in the third direction being separated between the two memory cells.

In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.

According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.

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Mie, Japan

Natsuki Fukuda