Rf Micro Devices, Inc.

Qorvo Us, Inc.

International Business Machines Corporation

Nathaniel Peachey

Swaminathan Muthukrishnan

Joseph Hubert Colles

Christian Rye Iversen

Jeffrey D Potts

Walter Anthony Wohlmuth

Ralph Christopher Nieri

Jason Yuxin Li

Muhammad Iqbal Chaudhry

Robert J Gauthier, Jr

Kiran V Chatty

Michel J Abou-Khalil

Chee Kwang Quek

Cody Hale

Carlos Gamero

Ralph Williamson

Aspects disclosed herein include trigger circuitry for electrostatic discharge (ESD) protection. In this regard, in one aspect, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. Trigger circuitry, which includes a voltage divider for example, divides a voltage spike between a supply rail and a ground rail to provide a trigger voltage. An ESD clamping circuitry is activated to discharge the voltage spike when the trigger voltage is determined to exceed an ESD threshold voltage, thus protecting the IC from being damaged by the voltage spike. By activating the ESD clamping circuitry based on the trigger voltage divided from the voltage spike, it is possible to adapt the ESD protection circuit to provide ESD protection based on different ESD threshold voltages, thus making it possible to deploy the ESD protection circuit on ICs having different ESD protection requirements.

Trigger circuitry for electrostatic discharge (ESD) protection

Aspects disclosed in the detailed description include an electrostatic discharge (ESD) protection circuit. In this regard, in one aspect, an ESD protection circuit is provided to protect an integrated circuit (IC) during fabrication and production. An ESD detection circuitry detects an ESD event by detecting a voltage spike between a supply rail and a ground rail exceeding an ESD threshold voltage. In response to detecting the ESD event, an ESD clamping circuitry is activated to discharge the ESD event, thus protecting the IC from being damaged by the ESD event. By detecting the ESD event based on the ESD threshold voltage, as opposed to detecting the ESD event based on rise time of the voltage spike, it is possible to prevent the ESD clamping circuitry from missing voltage spikes associated with a slow rise time or being falsely activated by a normal power-on voltage associated with a fast rise time.

Electrostatic discharge (ESD) protection circuit

An electrostatic discharge (ESD) protection circuit is disclosed. In this regard, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. In one aspect, an ESD voltage detection circuitry activates an ESD clamping circuitry when an ESD voltage associated with faster voltage rise time is detected between a supply rail and a ground rail. In another aspect, an operation voltage detection circuitry deactivates the ESD clamping circuitry when an operation voltage associated with slower voltage rise time is detected between the supply rail and the ground rail. By differentiating the ESD voltage from the operation voltage based on respective voltage rise times, it is possible to prevent the ESD clamping circuitry from missing the ESD voltage associated with the faster voltage rise time or being falsely activated by the operation voltage associated with the slower voltage rise time.

An electro-static discharge (ESD) protection circuit utilizes a gate-drain breakdown characteristic of high electron mobility transistors (HEMTs) in a dual stacked configuration to provide a discharge path for electro-static discharges, while having a minimal effect on the associated circuit which is being protected.

Clamp based ESD protection circuits

Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.

Local voltage control for isolated transistor arrays

The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.

Electro-static discharge power supply clamp with disablement latch

A circuit and method for electrostatic discharge (ESD) protection. The ESD protection circuit includes: a silicon control rectifier (SCR) connected between a first voltage rail and a second voltage rail; one or more diodes connected in series in a forward conduction direction between the first voltage rail and a source of a p-channel field effect transistor (PFET); a drain of the PFET connected to the SCR and connected to ground through a current trigger device; and a control circuit connected to the gate of the PFET.

Low leakage electrostatic discharge protection circuit

The present invention is a latching electrostatic discharge (ESD) protection circuit that enables and latches an ESD clamping circuit upon an ESD event, and disables and un-latches the ESD clamping circuit upon either a drop in the DC supply voltage below a defined threshold or a time-out. The time-out protects against effects of inadvertent latching or any anomaly in which the latching ESD clamping circuit does not un-latch. An ESD event is a voltage spike between the DC supply voltage and ground wherein the ESD clamping circuit applies a low impedance between the DC supply voltage and ground to dissipate the energy contained in the voltage spike, thereby protecting adjacent circuitry.

Unlatch feature for latching ESD protection circuit

The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance and a drain-to-gate resistance of the FET element and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element, a resistive element, a source-coupled level shifting diode, and a reverse protection diode. Therefore, the ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

Depletion-mode field effect transistor based electrostatic discharge protection circuit

The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance, a drain-to-gate resistance, or both of the FET element, and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element and a resistive element. Therefore, the single FET element ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

Enhancement-mode field effect transistor based electrostatic discharge protection circuit

Methods and apparatus for ESD protection of pseudomorphic high electron mobility transistor (pHEMT) circuitry are described. In one method, an ESD surge is detected at a trigger circuit. An ESD protection circuit is triggered. Current flow within the trigger circuit is limited and ESD energy is dispersed to a ground plane via the ESD protection circuit.

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Oak Ridge, NC, United States of America

Nathaniel Peachey