Microsoft Technology Licensing, LLC

Nathaniel L Lynch

Alessandro Forin

Richard Neil Pittman

Richard F Rashid

Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines whether the reconfigurable execution path (and/or which path) will handle that instruction. A content addressable memory may be used to determine the execution path when fed the instruction's operational code, or an arbiter and multiplexer may resolve conflicts if multiple instruction decode blocks recognize the same instruction. The execution path may be dynamically reconfigured, activated or deactivated as needed, such as to extend an instruction set, to optimize instructions for a particular application program, to implement a peripheral device, to provide parallel computing, and/or based on power consumption and/or processing power needs. Security may be provided by having the reconfigurable execution path loaded from an extension file that is associated with metadata, including security information.

Reconfiguration of execution path upon verification of extension security information and disabling upon configuration change in instruction extensible microprocessor

A post-compilation tool can rewrite executable images produced by a compiler. The tool can add extension definitions, insert extension-trigger instructions, and add a security signature. Operating system software may be notified of extension capabilities when loading the executable image, and may proceed to load an appropriate processor extension. The operating system software can manage availability of processor extensions on behalf of the applications.

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Nathaniel L Lynch