International Business Machines Corporation

Nathaniel Douglas Hieter

Alexander Joel Suess

David James Hathaway

Kerim Kalafala

Shyam Ramji

Frank Musante

Benjiman L Goodman

Anthony Correale, Jr

Ruchir Puri

Prabhakar Nandavar Kudva

Debjit Sinha

Todd Edwin Leonard

Samuel I Ward

Adam P Matheny

David Shing-Ki Kung

Benjamin Neil Trombley

Subhrajit Bhattacharya

Leon Stok

Adil Bhanji

Ofer Geva

Peter James Osler

Jeremy T Hopkins

Veena S Pureswaran

Bijian Chen

Douglas Keller

Paul M Campbell

Jeffrey S Piaget

William E Dougherty

Daniel Arthur Gay

Charles Kenneth Hines

Carry out an initial wire-length-driven placement for an integrated circuit design embodied in an unplaced netlist, using a computerized placer, to obtain a data structure representing initial placements of logic gates. Identify at least one timing-critical source-sink path between at least one pair of source-sink endpoints in the data structure representing the initial placements. Create a new pseudo two-pin net for each pair of the at least one pair of source-sink endpoints to create an updated netlist. Carry out a revised wire-length-driven placement on the updated netlist to obtain a data structure representing revised placements.

Path-based timing driven placement using iterative pseudo netlist changes

A system to develop an integrated circuit includes a latch identifier module to identify a first child latch placed at a first location in a first child macro of a parent macro and a second child latch placed at a second location in a second child macro of the parent macro. The second child latch is located away from the first child latch. The system further includes a latch location optimization module and a latch placement module. The latch location optimization module determines a target timing parameter threshold and determines a first actual timing parameter. The latch placement module changes the first location of the first child latch and/or the second location of the second child latch to generate an optimized parent macro based on the changed locations. The latch location optimization module re-executes the latch optimization process to determine a second actual timing parameter based on the changed locations.

Out-of-context feedback hierarchical large block synthesis (HLBS) optimization

Methods and apparatus for creating an improved VLSI design. In-context timing analysis of a nominal VLSI design is performed and at least one assigned apportionment adjustment is determined for a sub-block of the nominal VLSI design. One or more slack adjustments are derived for at least one port of the sub-block based on the at least one apportionment adjustment and the one or more slack adjustments are applied to the in-context timing analysis to simulate a post optimization version of the sub-block. The in-context timing analysis is repeated using the one or more applied slack adjustments to generate the improved VLSI design.

Apportionment aware hierarchical timing optimization

A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.

Leverage cycle stealing within optimization flows

A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.

Optimizing placement of circuit resources using a globally accessible placement memory

A system and method perform global routing during integrated circuit fabrication. The method includes performing a design change in a portion of an integrated circuit design using a processor, determining whether the design change requires rerouting, and requesting a global routing lock based on determining that the design change requires the rerouting. The method also includes a router providing control of the global routing lock to one of two or more of the threads that request the global routing lock, and performing global routing for all of the two or more of the threads in parallel. A physical implementation of the integrated circuit design is obtained.

Parallel incremental global routing

Managing virtual boundaries to enable lock-free concurrent region optimization, including: receiving a model of an integrated circuit ('IC'); dividing the model into a plurality of regions, wherein none of the plurality of regions overlap with another region; assigning each of the plurality of regions to a thread of execution, wherein each thread of execution utilizes a shared memory space; and optimizing, by each thread in parallel, the assigned region.

Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit

A method of performing a static timing analysis based on slack values to verify and optimize a logic design includes: selecting one or more circuits within the logic design having at least two inputs taking on a known value; identifying a critical input that controls an output arrival time of the selected circuit from among the inputs that take on the known value; determining one or more non-critical input of the circuit a required arrival time based on the difference between the arrival times of the critical and non-critical inputs; and computing the slack at a critical input based on the difference between the AT of the critical and non-critical inputs. The design optimization based on the slack defined by arrival time differences preferably uses a reverse merge margin design metric. The metric determines the exact required amount of improvement in the input arrival time of non-critical signals of a clock shaping circuit.

Method for enabling multiple incompatible or costly timing environment for efficient timing closure

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Clinton Corners, NY, United States of America

Nathaniel Douglas Hieter