International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Renesas Electronics America Inc.

Microsemi Corporation

Nathaniel C Berliner

Kangguo Cheng

William R Tonti

Toshiharu Furukawa

Douglas C La Tulipe, Jr

Kam-Leung Lee

Tenko Yamashita

Veeraraghavan S Basker

Nicolas J Loubet

Jed Hickory Rankin

Christian Lavoie

Robert Russell Robison

Sanjay C Mehta

Pranita Kulkarni

Ahmet Serkan Ozcan

Balasubramanian S Haran

Emre Alptekin

Johnathan E Faltermeier

James J Demarest

Hyun-Jin Cho

Lisa F Edge

Paul Andrew Ronsheim

Kingsuk Maitra

Dumitru Sdrulla

Zhengmao Zhu

Jason E Cummings

Amaury Gendron-Hansen

Bruce Odekirk

Toyoji Yamamoto

Raymond J Donohue

A semiconductor device constituted of: a semiconductor layer; and a field layer patterned on said semiconductor layer, said field layer constituted of material having characteristics which block diffusion of mobile ions and maintain structural integrity at activation temperatures of up to 1200 degrees centigrade.

Semiconductor device with improved field layer

A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFET fins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.

Conformal doping for FinFET devices

An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.

Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness

A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.

Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness

A method for forming a raised silicide contact including depositing a layer of silicon at a bottom of a contract trench using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide, a width of the silicide and the contact trench are substantially equal; heating the silicide including the silicon layer to a temperature from about 300&#xb0; C. to about 950&#xb0; C. in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.

Raised silicide contact

A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.

Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion

A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.

Dual metal fill and dual threshold voltage for replacement gate metal devices

Growing community of inventors

Albany, NY, United States of America

Nathaniel C Berliner