Arm Limited

Nathan Yong Seng Chong

Richard Roy Grisenthwaite

Thomas Christopher Grocutt

Milosch Meriac

Yasuo Ishii

Frederic Claude Marie Piry

Peter Richard Greenhalgh

Matthew James Horsnell

Ian Michael Caulfield

Albin Pierrick Tonnerre

Alastair David Reid

Matthias Lothar Boettcher

Grigorios Magklis

Dominic Phillip Mulligan

An apparatus is described with support for transactional memory and load/store-exclusive instructions using an exclusive monitor indication to track exclusive access to a given address. In response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, any exclusive monitor indication previously set for the load target address is cleared. In response to a load-exclusive instruction, an abort is triggered for a transaction for which the given address is specified as one of its working set of addresses. This helps to maintain mutual exclusion between transactional and non-transactional threads even if there is load speculation in the non-transactional thread.

Handling load-exclusive instructions in apparatus having support for transactional memory

A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.

Encoding of input to storage circuitry

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Cambridge, United Kingdom

Nathan Yong Seng Chong