Cypress Semiconductor Corporation

Intel Corporation

Texas Instruments Corporation

Nathan Y Moyal

Mark J Marlett

Bertrand Jeffery Williams

Mark R Gehring

Dana Jon Olson

Steven C Meyers

Steve Meyers

David Gordon Wright

Jonathon C Stiff

Brian G Kirkland

Tao Peng

James Robert Feddeler

Jerry Doorenbos

Michael L Duffy

Brent R Jensen

Lawrence Ragan

Stephen O'Connor

Russell R Moen

Eric P Mitchell

Ronald F Cormier, Jr

Phillip J Kruczkowski

Michael Ren Kent

Jaideep Prakash

Raha K Prasun

A system and method for determining position information. The method includes selecting a column, a first row, and a second row of a capacitive sensor array. The first row and second row intersect with the column of the capacitive sensor array. The method further includes measuring a differential capacitance between the first row and the second row and utilizing the differential capacitance in determining a location of an object proximate to the capacitive sensor array.

System and method to measure capacitance of capacitive sensor array

An apparatus is provided. The apparatus comprises a second layer disposed over a first layer. Each of the first and second layers have a set of detection electrodes that are spaced apart and electrically isolated from one another and an associated set of interleavers. Each interleaver is located between adjacent detection electrodes from its associated the set of detection electrodes, and each set of interleavers also includes a pair of complementary interleaving electrodes coupled to those that are electrically coupled to the adjacent detection electrodes from its associated set of detection electrodes. The detection electrodes and interleaving electrodes are also substantially transparent to visible spectrum light.

Capacitive touch panel having improved response characteristics

A capacitance measurement sensor, having a voltage subtractor that rejects common signals between the columns or rows of a touch sensor matrix depending on which are driven and which are being sensed, is described.

Multi-touch sensing method

A system and method for measuring capacitance of a capacitive sensor array is disclosed. Upon measuring the capacitance, position information with respect to the sensor array may be determined. A column, a first row, and a second row of a capacitive sensor array may be selected. The first row and the second row intersect with the column of the capacitive sensor array. A differential capacitance between the first row and the second row may be measured. The differential capacitance may be utilized in determining a location of an object proximate to the capacitive sensor array.

In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.

Tri-stating a phase locked loop to conserve power

One embodiment includes a system configured to identify a preferred channel for radio communication from a plurality of consecutive integer frequencies including preferred channels and non-preferred channels, the system further to generate a plurality of radio channels corresponding to a plurality of consecutive integer frequencies based on a generation of reference frequencies, identifies preferred channels and non-preferred channels from the plurality of radio channels, where frequency synthesizer settling times of the preferred channels are faster than frequency synthesizer settling times of the non-preferred channels, scan the preferred channels for radio activity, select one of preferred channels responsive to the scanned radio activity; and utilize one of the reference frequencies to generate a radio frequency corresponding to the selected one of the preferred channels.

Radio communication device and method

Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Method and circuit for rapid alignment of signals

A system and method of loading a programmable counter includes storing a first digital divide value in a register. The first digital divide value is then loaded from the register to a programmable counter. The method further includes writing a second digital divide value to the register at a time responsive to a time remaining to complete a counting cycle of the programmable counter.

System and method of loading a programmable counter

An improved circuit and method is described herein for extending the usable frequency range of a high performance, narrow band phase locked loop (PLL) device. For example, the improved circuit and method may perform a calibration sequence for calibrating an LC-type voltage controlled oscillator (VCO) immediately before or during operation of the PLL device. Unlike previous methods, the calibration sequence described herein provides a fast and convenient method for extending the usable frequency range of a PLL by shifting the center frequency of the LC-type VCO to a desired frequency. For example, the VCO center frequency may be incrementally shifted (e.g., either high or low) to compensate for the actual environmental conditions in which the PLL is used (i.e., to compensate for specific process, voltage, and temperature conditions). Once the calibration bits are set to the desired frequency, the calibration sequence is disabled, and the appropriate calibration bit values are applied to the VCO during normal operation of the PLL.

Circuit and method for extending the usable frequency range of a phase locked loop (PLL)

A method and apparatus to synchronize a boost signal. The apparatus includes a boost circuit and a synchronization circuit. The synchronization circuit is coupled to the boost circuit. The boost circuit generates an unsynchronized boost signal to boost a voltage signal from a first voltage to a second voltage. The synchronization circuit synchronizes the unsynchronized boost signal with a reference signal to generate a synchronized boost signal.

Synchronized boost signal apparatus and method

A circuit and method for providing a periodic clock signal, such as a high frequency clock signal. In one example, the circuit may include a phase locked loop circuit having a voltage controlled oscillator, the voltage controlled oscillator having a voltage input, a calibration input, and a clock signal output; and a logic circuit for dynamically calibrating an operating frequency of the phase locked loop during operation of the phase locked loop. In one embodiment, the logic circuit may compare an input voltage into the voltage controlled oscillator against a reference voltage, and if the input voltage is lower than the reference voltage, the logic circuit decreases the operating frequency of the phase locked loop circuit. The logic circuit may compare an input voltage into the voltage controlled oscillator against a reference voltage, and if the input voltage is higher than the reference voltage, the logic circuit increases the operating frequency of the phase locked loop circuit.

Circuit and method for improving frequency range in a phase locked loop

The present invention adds an additional feedback loop to a phase locked loop (PLL). The additional feedback loop detects if the actual output frequency of the PLL is above or below the desired output frequency. If the actual output frequency is above the desired output frequency a signal is added to the forward path of the PLL to decrease the frequency of the PLL oscillator. If the actual output frequency is below the desired output frequency a signal is added to the forward path of the PLL to increase the frequency of the PLL oscillator.

Method of improving lock acquisition times in systems with a narrow frequency range

A Phase Locked Loop (PLL) that has a substantially constant gain over a wide frequency range. The frequency range over which the PLL operates is divided into a number of frequency sub-ranges. The circuit includes a mechanism for adjusting the loop gain profile as the PLL moves from one frequency sub-range to another. When the PLL switches to a new frequency sub-range, the loop gain profile is adjusted to a pre-established value. Changes of frequency within each sub-range are then accomplished with the loop gain varying within a pre-established range.

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West Linn, OR, United States of America

Nathan Y Moyal