Applied Micro Circuits Corporation

Nathan Y Elnathan

Alexander Joffe

Ilan Pardo

Tasks are dynamically allocated to process packets. In particular, packets of data to be processed are assigned a packet identification. The packet identification includes a lane and a packet sequence number. The term 'lane' as used herein refers to a port number and a direction (i.e. ingress or egress), such as Port 3 Egress. A set of resources (e.g., registers and memory buffers) are associated with each lane. The task is allowed to access resources associated with the lane. In some embodiments, a task may change the port that it services and use the resources associated with that port.

Dynamic allocation of packets to tasks

Tasks are assigned to process packets, but the tasks may not process the packets in the order in which the packets were received. Thus, the order of the packets may be lost during processing. The packets, however, should still be transferred in the order in which the packets were received. Therefore, reordering is performed. In particular, the reordering is performed by having tasks write commands for packets into command buffers of a command queue based on a packet sequence number of a packet matching a current sequence number associated with the buffer and by reading commands for consecutive packets in order by passing from one command buffer to another command buffer. With the command buffers in the command queue being written and read in this manner, the packets are 'reordered' so that they are transferred in the order in which they were received.

Reordering of out-of-order packets

Multiple attempts are made to identify an entry in a cache. For example, a first attempt uses a RAM-based addressing structure (such as the above-described table) and a second attempt (on failure of the first attempt) uses a CAM-based addressing structure. The RAM-based addressing structure is faster than the CAM based-addressing structure, and in cases of a hit on the first attempt, cache performance is based on RAM cycle time rather than CAM cycle time. On the other hand, a miss on the first attempt does not mean that the data is not present in the cache. Instead, a second attempt using the CAM in the traditional manner finds the data if present in the cache.

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Nathan Y Elnathan