Silego Technology Inc.

Dialog Semiconductor (uk) Limited

Nathan Willis John

John Othniel McDonald

Horst Knoedgen

Ambreesh Bhattad

Vikas Vinayak

Jay Li

David Kuneth Chow

Sidney Chan

David Kun-Teh Chow

A method of authenticating a second electronic device at a first electronic device, the method comprising: providing at the second electronic device a memory, the memory comprising a first memory portion which has restricted access and is readable only when a first secret key is presented to the second electronic device; sending the first secret key from the first electronic device to the second electronic device; in response, sending a second secret key stored in the first memory portion from the second electronic device to the first electronic device; and authenticating the second secret key at the first electronic device.

Method of authenticating a device

A comparator system and a method for comparing an input signal and a reference signal are presented. The system has a controller to adjust a rising output delay and/or a falling output delay of a system output signal. The system output signal is dependent on the comparison between the input signal and the reference signal. This system provides a more efficient comparator with reduced power consumption whilst still providing the required rising output delay and falling output delay for a given application. Techniques used in prior art will always resort to running the comparators at a speed that supports the speed requirements in the worst case conditions and does not exploit any asymmetries in the required rising output delay and falling output delay for a given application. When these asymmetries are exploited, further increases in power efficiency can be achieved.

Comparator system

A switching circuit and a method for providing a switch array having an on resistance is presented. The switch array has a plurality of switches, where each switch is arranged to be in different configuration states. The states include an enabled configuration and a disabled configuration. The switching states include an on state and an off state. Each switch is held in the off state when in the disabled configuration. Control circuitry sets the switches to either the enabled configuration or the disabled configuration, and a memory element coupled to the control circuitry and arranged to store configuration data for setting the configuration state of each of the switches. The control circuitry sets the configuration state of the switches based on a signal received from the memory element. The on resistance of the switch array depends on the switching state of the switches and their individual on resistances.

Switching circuit

A security integrated circuit is disclosed. In some embodiments, the security integrated circuit comprises metal configured memory that stores a first portion of each of a plurality of keys, programmable memory that stores a second portion of each of the plurality of keys, and an interface for connecting to an external authentication system. The metal configured memory and programmable memory store a prescribed finite number of host keys and matching device keys. In response to a received host key from the external authentication system, a matching device key is provided by the security integrated circuit.

Security integrated circuit

Various techniques for dynamic power FET switching are disclosed. In some embodiments, a device comprises an array of two or more independently switchable power MOSFETs that are configured to sense current in a high current mode and a low current mode as well as circuitry for automatically switching from the low current mode to the high current mode when sensed current is above a threshold to switch to the high current mode.

Growing community of inventors

Morgan Hill, CA, United States of America

Nathan Willis John